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chip_maker

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Everything posted by chip_maker

  1. Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see in editor "class myenv extends uvm_env;" I would Say: "class" type: myenv Say:"extends uvm_env;" For GUI usage, tool vendors/users could come up with a number of useful features similar to keyboard shortcuts. These features may be implemented both on Windows and Linux platforms. (Hope in few years engineers are able to dictate their code into a tool and debug it too! Also wish there is research on use of various HCIs for EDA) Thanks for reading my request! Regards, Kal Gandikota P.S.: I used windows speech recognition to write this e-mail as I am suffering from wrist pain. Please kindly ignore grammar mistakes.
  2. I had to add explicit predictor. It calls the sample function. What is the reason sampling is not called for auto prediction? Kal
  3. Hello, Ralgen is being used to generate UVM regmodel with address map coverage. I see the corresponding constructs. However when on simulating, the tool shows zero percent coverage. Wonder what I might be missing. Do I need to use sample() function explicitly? If so, how can I use it with pre-built UVM sequences? Kal In my uvm test, I have the following code: uvm_reg::include_coverage("*", UVM_CVR_ALL); super.build_phase(phase); endfunction : build_phase // void task run_phase(uvm_phase phase); super.run_phase(phase); void'(sve.m_spiup_regmodel.set_coverage(UVM_CVR_ALL)); //create vseq //run vseq endtask : run_phase
  4. I'm using Mentor's Questa for simulation. I don't see 'set_covergroup' command. By the way the report does include per_instance... For ralgen I used the following command: ralgen -l sv -t Mychip__Bus_2013_02_28_r0 -uvm -c a ralfconv.ralf -o ral_Mychip__Bus_2013_02_28_r0.svh To get cover report, I used the following command: coverage report -detail -cvg -comments -option -file fcover_report.txt Here's extract from log: Covergroup instance \/mychip_pkg::ral_block_Mychip__Bus_2013_02_28_r0_spi_module_1::cg_addr 0.0% 100 ZERO option.name=\/mychip_pkg::ral_block_Mychip__Bus_2013_02_28_r0_spi_module_1::cg_addr option.weight=1 option.goal=100 option.comment= option.at_least=1 option.auto_bin_max=64 option.cross_num_print_missing=0 option.detect_overlap=0 option.per_instance=1 option.get_inst_coverage=0 Coverpoint sys_clk_pll_reset_reg 0.0% 100 ZERO covered/total bins: 0 1 missing/total bins: 1 1 option.weight=1 option.goal=100 option.comment= option.at_least=1 option.auto_bin_max=64 option.detect_overlap=0 bin accessed 0 1 ZERO
  5. provides_responses=1 may solve the problem Kal
  6. In the following code, I cannot hierarchically refer a function in scoreboard from sequence. I have to first get the scoreboard handle and then call function using the handle. The following does not work: uvm_test_top.env.my_env0.my_sb0.disable_scoreboard(0); The following works handle_my_sb0.enable_scoreboard(1); What am I missing something in the first case? Thanks, Kal =========== class my_test2_vseq extends my_base_test_vseq; uvm_component handle_sb; my_scoreboard handle_my_sb0; `uvm_object_utils(my_test2_vseq) `uvm_declare_p_sequencer(my_virtual_sequencer) function new(string name="my_test2_vseq"); super.new(name); handle_sb = uvm_top.find("*my_sb0"); `uvm_info("",$psprintf("handle_sb %s", handle_sb.get_full_name()),UVM_LOW) $cast(handle_my_sb0, handle_sb); `uvm_info("",$psprintf("handle_my_sb0 %s", handle_my_sb0.get_full_name()),UVM_LOW) endfunction : new task body(); #200ns //uvm_test_top.env.my_env0.my_sb0.disable_scoreboard(0); //<- Does not work handle_my_sb0.enable_scoreboard(1); // Works #10000ns ; endtask:body endclass:my_test2_vseq
  7. Hi, I am having code like this uvm_tlm_analysis_fifo#(an_item) before0_fifo an_item before0_trans; In a task I have the following code before0_fifo.try_get(before0_trans); `uvm_info(get_type_name(), $psprintf("Inside task comparer3: Transfer collected :\n%s", before0_trans.sprint()), UVM_FULL); The execution is returning "NULL pointer dereference." when there are no objects in 'before0_fifo'. I was expecting try_get to be 1. Non-blocking 2. if there are no objects in before0_fifo, then before0_trans should have had previouly gotten value. (As per the UVM Class Reference manual under section 'uvm_tlm_if_base #(T1,T2)', the try_get description reads "If a transaction is immediately available, then it is written to the output argument and 1 is returned. Otherwise, the output argument is not modified and 0 is returned" ) Please let me know what I'm missing. Regards Kal
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