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  1. UVM Reference Flow Version 1.1



    The UVM Reference Flow version 1.1 has been updated to align with the Accellera uvm-1.1 release (uvm-1.1a). It applies the Universal Verification Methodology (UVM) to a Block and Cluster Verification in a SoC Design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block, a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO, Power Controller, Timers etc…). This contribution is not approved or endorsed by Accellera but may be of interest to UVM users as is true of other contributions. What’s New : This release of the UVM Reference Flow is completely aligned with the latest uvm-1.1 production library from Accellera and demonstrates the latest features including: - global resource database for configuration mechanism - UVM_REG methodology for register verification. The UVM_REG package is a part of uvm-1.1 release. This release also includes a UVM e Reference Flow which applies the Universal Verification Methodology in e (UVM-e developed by Cadence) to the same block and cluster level Verification of UART and APB subsystem. The sample verification environments (both block and cluster level) contain UVCs based on eRM as well as using UVM-e. Both eRM and UVM-e compatible UVC's can be nicely integrated together and can work seamlessly. Thus, it ensures that all existing eRM compliant environments need not to be re-coded to work with an UVM compatible environment. Usage of the UVM-e Scoreboard package is also included in this release. The UVM Reference Flow design is based on an Ethernet Switch System-on-Chip (SoC). The SoC has the following key design components 1. An Opencores Open RISC Processor 2. Opencores Ethernet Media Access controller (MAC) 3. AMBA AHB network interconnect 4. Address Look up table (ALUT) 5. Support and Control functions. For instance power management and peripherals like UART, SPI, GPO, timer etc 6. On-chip Memories and memory controller The UVM Reference Flow also includes the following key verification components 1. AMBA AHB UVC (SV & e) 2. AMBA APB UVC (SV & e) 3. UART UVC (SV & e) 4. GPIO UVC (SV & e) 5. SPI UVC (SV & e) 6. Register Memory Package (uvm_reg) from uvm-1.1 library 7. UVM-e scoreboard Please look at the UVM Reference Flow user guide which can be found at For SV flow : <UVM Reference Flow Installation area>/doc/uvm_flow_topics/uvm_sv/uvm_sv_ref_flow_ug.pdf for more details. For e Flow : <UVM Reference Flow Installation area>/doc/uvm_flow_topics/uvm_e/uvm_e_ref_flow_ug.pdf for more details. Release Version :1.1 The UVM Reference UVM Reference Flow 1.1 release is tested with UVM 1.1 Production Library (uvm-1.1) (from Accellera) and Incisive Enterprise Simulator (IES) 11.1 It should be possible to run the UVM Reference Flow on any IEEE 1800 and 1647 Compliant Simulator which supports UVM. For more information about using the UVM Reference Flow please contact uvm_ref@cadence.com.
  2. Hi Arjun, The UVM reference flow has design and verification components that are opensource. It should work with any IEEE 1800 Compliant Simulator which supports UVM. In this package the flow scripts are based on Cadence Incisive Enterprise Simulator (IES). Thanks, Swami