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Adam Sherilog

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About Adam Sherilog

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  1. You have a need for speed. Everyone does. But not a small need. You have a big need. Not a 2X need. A much bigger need. The kind of need that can only be satisfied with Palladium, the best hardware accelerator available. Axel Scherer, my Cadence brother, recorded this video to show how you can run your UVM environment in simulation and acceleration. Spend 5 min to learn how you can quench your need for speed. http://youtu.be/2S4NIrOT9XE?list=PLYdInKVfi0KZqWOWeDTa58tuBD-5S7HQC Fast simulation. Fast acceleration. Fast post. Enjoy. =Adam Sherer, Cadence
  2. Welcome to the UVM 1.2 Public Review

    Aliu - we don't have HTML yet. Its is something we are considering but we don't have a plan yet. However, that is very good input! Leo - we are trying to update the user guide. We should have more information on what can be done after the next UVM working group meeting in early July. =Adam
  3. On behalf of the UVM Working Group (UVMWG), welcome to the public review forum for UVM 1.2. It includes enhanced messaging, improvements to the register layer and other features. As you use it we encourage you to post comments and suggestions to this forum. We've staffed the forum with some of the UVMWG experts to answer your questions and bring your suggestions into the committee. We will be analyzing them as part of an effort to take UVM 1.2 to the IEEE by October 1, 2014. You can find a direct Class Reference link here: http://www.accellera.org/downloads/standards/uvm/UVM_Class_Reference_Manual_1.2.pdf You can find a direct tarball link here: http://www.accellera.org/downloads/standards/uvm/uvm-1.2.tar.gz Thank you for your help and we look forward to some interesting technical discussions. Regards, Adam Sherer, UVMWG Secretary
  4. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  5. Hi, I think this question, especially for a particular set of product licenses, is best answered by Cadence support. But the IES vs IUS I can answer here. IES, the Incisive Enterprise Simulator, has two product configurations L and XL. The IES-XL is the one you should use if you previously purchased IUS (Incisive Unified Simulator). IES-XL is a whole superset of IUS and can run any scripts created using IUS. =Adam Sherer, Incisive Simulation Product Manager
  6. Folks, We had some complaints about this thread. If there is truly a tools-related issue, that should be directed to the vendor's support team. We shouldn't use these forums to suggest that users of vendor X would be better off with vendor Y. If a vendor has something to promote, that should be handled in the "Simulator Specific" or "Commercial" forums. =Adam Sherer Accellera Promotions Committee Vice-Chair
  7. The DVClub meeting September 9 is 100% dedicated to you all reading this forum -- UVM and SystemVerilog. We'll have four topics in this fast-moving event: Update from the Accellera UVM Working Group UVM Register Modelling: Advanced Topics SystemVerilog Scheduling Semantics Advanced Scoreboarding Techniques Using UVM You can register for the event here: http://dvclubsept2013.eventbrite.com/#! On behalf of the other presenters, we are looking forward to seeing or hearing you there! =Adam Sherer, UVM WG Secretary
  8. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence
  9. UVM 1.1c is available for immediate download

    You can also find the release notes on the accellera.org site. The 1.1c notes show the delta from 1.1b. By Accellera rules, the [abc*] releases do not change the standard. =Adam
  10. Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple language in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. This solution was updated several times during the past four years to remain synchronized with UVM and add new functionality. On Thursday October 25 at 9a PDT we'll review the solution and discuss new features. Join us through this link: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home =Adam Sherer, Cadence
  11. It's here! The UVM 1.1c release is now available for immediate download on the Accellera Website at http://www.accellera.org/downloads/standards/uvm. Enjoy! =Adam Sherer, Accellera VIPTSC Secretary
  12. UVM SystemVerilog Basics in 24 short videos

    And just when you thought all of the above goodness was too good to be true, we have even more! UVM has been growing by leaps and bounds in China so we translated the video shorts into Chinese! Do to some restrictions in China, we have made the videos available on two sites: Link to YouTube Playlist (Chinese) Link to YouKu Playlist (Chinese) Link to YouTube Playlist (English) Link to YouKu Playlist (English) We would also like to introduce our third twin :-), Yi-Shiun Lin who did the work to translate these videos. Thank you! =Adam Sherilog on behalf of both of his twins Axel and Yi-Shiun
  13. UVM SystemVerilog Basics in 24 short videos

    Just when you thought 24 videos about UVM were enough, we added more! This video walks you through the UVM Class Library pointing out key aspects that are important to all UVM developers. It's your coffee break, so grab a fresh cup and enjoy! http://www.cadence.com/Community/blogs/fv/archive/2012/07/16/uvm-systemverilog-class-library-overview-video-inspired-by-1600-cowbells-in-action.aspx =Adam Sherilog on behalf of Cadence's prolific video presence, and my twin brother, Axel Scherer
  14. The Accellera Systems Initiative Verification IP Technical Subcommittee (aka UVM) has approved the UVM 1.1b for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. We have also had numerous requests to make the release notes and user guide available both inside and outside of the tarball. You can find direct links to both documents on the downloads page and here: UVM 1.1b tarball UVM 1.1b release notes UVM 1.1 user guide UVM 1.1b closes more than 40 Mantis items and represents the combined contributions from multiple committee members. The Chairs would like to thank the worldwide community for their use of UVM and their timing reporting of bugs. =Adam Sherer, VIPTSC (UVM) Secretary
  15. All, Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher. The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community. http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE The initial set of topics include the following and we expect to do more in the future: Introducing UVM Example DUT UVM Environment Interface UVC Collector Monitor Sequence Item Sequence Driver Sequencer Agent Agent types Interface UVC environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases Objections Virtual Interface =Adam Sherilog Cadence Verification Product Director
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