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shubham_v

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  1. Hi, Please check the above thread. I am facing few hiccups while recording a waveform in tlm.I have tried for the alternate ways as mentioned in this topic "waveform tracing in tlm". Can anyone guide me through this ? Thanks & regards, Shubham
  2. hi @Eyck, I implemented the example as mentioned by you.But i am facing few problems to build it. These are the steps which i had follwed. 1.I am using vs2015 for compiling,i used all sv4tlm files that has .h file name and included them in my main file .cpp and defined them also.You had mentioned under scc:: i need o instantiate,but when i had gone through the code ,found that it will come under namespace sv4tlm::,so made changes accordingly. 2.when i compiled my .cpp file,i was facing out with missing headers of scv.h file,as i was not aware about the scv files,after exploring and through accelera i included scv files. I made changes wrt to lib and source directories and it looks like the attached image. 3.By follwing al of this, i got the other error of scv.lib not found even though i had mentioned scv.lib;systemc.lib along with additional dependencies in linker properties.I had cross checked the properties by seeing one of the examples of scv . Along with this ,the instantiated part code is as follows, scv4tlm::tlm2_recorder_module<> inst_mod("rec_module"); inst_mod.target(targ->t_socket); inst_mod.initiator(init->i_socket); scv_startup(); scv_tr_text_init(); scv_tr_db db("my_db.txlog"); scv_tr_db::set_default_db(&db); top t ("dut"); sc_start(200,SC_NS); But after follwing these steps,i was not succesfull in my attempts. Can you please help me regarding this problem,where exactly is the issue.? if i have made any mistakes in copying the files or in some other part of the code then can you please elaborate the steps to follow? Thanks in advance. Regards, shubham
  3. Hi @David Black, Either of them i.e tracing or recording is fine.I want to cross check the triggering of clocks and at what time exactly the transfer of data takes place in a waveform. Can you please throw the light on how to record these transactions ? Is there requirement of any new software ? what will be the approach for recording? In the above example which i had shared,i can see the waveforms of my clock but the transaction attributes(mainly data , address & cmd) i cant see. Thanks & regards, Shubham
  4. Hi, I wanted to know ,is it possible to trace waveforms in tlm.I tried for alternate ways as it was done in system c earlier also.But i wasnt successful in my attempts. One of the way i tried was by using the init_socket and targ_socket again in top which is completely wrong i guess.I cant reuse the tlm sockets again for my instantiated modules. int sc_main(int argc,char* argv[]) { initiator* init; target* targ; tlm_utils::simple_initiator_socket<initiator>i_top_socket; tlm_utils::simple_initiator_socket<target>t_top_socket; init = new initiator("init"); targ = new target("targ"); init->i_socket(i_top_socket); targ->t_socket(t_top_socket); sc_clock clk1("clk1", 10, SC_NS, 0.5); sc_clock clk2("i_t_clk", 20, SC_NS, 0.5); init->i_socket.bind(targ->t_socket); init->ext_i_clk(clk1); targ->int_t_clk(clk2); sc_trace_file* tf = sc_create_vcd_trace_file("b_transport"); sc_trace(tf, clk1, "ext_clk"); sc_trace(tf, clk2, "t_clk_internal"); sc_trace(tf, init->i_socket, "i_socket"); sc_trace(tf, targ->t_socket, "i_socket"); sc_start(200, SC_NS); sc_close_vcd_trace_file(tf); return 0; } The other way i tried was getting the arguments not matching error i.e arguments support sc_signal type and i am using tlm types.I kno that the compiler is telling the difference in arguments,but whats the alternate solution for this problem ? Can anyone please tellme where am i going wrong and how to trace the transaction exactly ? And Is it really possible to trace waveform in tlm ? Thanks & regards, Shubham
  5. Hi @Eyck, Yes for clock based events,this would be much better approach and it worked. Thanks a lot for your help 🙂 Regards, Shubham
  6. Hi @eyck, As far as lrm is concerned with,i can see sensitive list in sc_thread.It is as follows , So, i had missed this concept of posedge event. When i included pos_edge event ,i was able to controll the process. Just to cross check ,i included only wait() without any arguments in second thread,during that time my second thread was not running.So ,process is controlled by clock now. Yes, i had forgotten to delete the pointer created payload.Thank you for pointing it out. Regards, Shubham
  7. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering by clocks.? do i need to look out for other interface method in tlm or should i go back to system c interface approach ? Please help me out with this. Thanks & regards, Shubham Ps:- I am attaching the code along with the block diagram below,please let me know the solution for it.The block diagram represents 2 blocks of initiator and target modules with clock supplied. Iam able to compile and run the code succesfully,if you get any error while compiling i might have done mistake while copying. initiator.h.txt main.cpp.txt target.h.txt initiator2.h.txt target2.h.txt top.h.txt
  8. Hi @AmeyaVS, Yes,i know that new post has nothing new content.The whole idea was to just repost it and i needed answer for the folllow up question which i had mentioned in my previous thread. Sorry for the repeated content,I was not knowing how to revoke the older thread. Thanks & regards, Shubham
  9. Hi, Its a follow up question of my previous thread.I am having a task to use clocks in a tlm based module. Please have a look at the below thread , Thanks & regards, Shubham
  10. thank you david,eyck. I will try again to implement a simple example in tlm with the usage of clocks. But if there is a spec. condition to declare clocks ,then what would be the approach ? Should i go back to systemc interfaces or continue with the tlm ? Regards, Shubham
  11. Hi, I was having few questions regarding clock usage in tlm.These are as folllows:- 1.I wanted to know whether we can supply clock to initiator and target modules. 2.If it can be used ,then how to do we need need to connect to modules.Like instantiate clock in top module and how should we do port or named mapping ? If not,then why its not used ? Because i havent come across any examples in tlm which uses clocks. 3.If we are using blocking interface then using wait statement,just that data doesnot get overidden. And if its a case of nb_interface then we are using delay statements . My question here would be,can i create system clock input port and connect them ? I had tried but i had got a failed port mapping error message. Thanks & regards, Shubham
  12. ok david,there was actually some copying mechanism done in the target side which i was missing to see it,so i had got this doubt. But its clear now,general modelling errors can be set,and not the other one. Thank you david 🙂
  13. Hi, Its just a follow up question on blocking_interface.It is as follows- As we will be having up a memory in target side and it will be executed on its own and assume all space of int[255] array will be filled. Now ,if a write command is generated from the initiator side and the target realises that there is no space to write or better to say the space is already written,den what would be the response from the target side.Does it send a "FAILED TRANSACTION" error or will there be some sort of alternate way to execute the command ? Thanks & regards, shubham ps-I am attaching the link of my previous thread,in which i had mentioned about my understanding of b_transport interface.
  14. Hi david, I seriously appreciate your time and effort to answer my question in such a nice way. Thanks a lot,david. Regards, Shubham
  15. Hi , I was having doubt over using these interfaces defined in diff languages. I am comparing 3 of the inerfaces below as follows: SYSTEM VERILOG - In system verilog as much as i am aware about,we will be declaring a common interface and give the direction for inputs & outputs via modports and driving the blocks with a common clock. SYSTEM C -In system c, we will be inheriting interface from sc_interface,declaring the type of operation required ,that is in turn defined in the required type of channel and then executed. TLM- There are diffrent type of predefined interfaces,which will be used depending on our requirement such as b_transport for LT MODEL,and nb_transport for AT MODEL. My question is, in interfaces we are defining the inputs and ouputs in sys.verilog and connecting them.Then what about in system c and tlm ? Is there any possibility of declaring the inputs in system c and tlm interfaces? What i think is ,as these are already predefined ,so we dont need to alter anything over there in the interfaces. And even if we got to change any thing in the interfaces,complexity might increase ? This is the confusion which i am getting when working with them,please let me know how exactly are they differeing during defining the inputs and outputs . Thanks in advance. Regards, Shubham
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