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sas73

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  1. Thanks @dave_59. That would be the easiest way but in my case I want to verify that the message fields are what I expect, not only that a report has been produced. I ended up pushing the report message to a queue and then pop it in my test to verify the fields.
  2. Thanks @kirloy369! Looks more UVM idiomatic. Doesn't necessarily make it a better solution that what has been proposed before but I wanted to start by trying out how it was intended to be done.
  3. Thanks for the reply David. This is similar do what has been done in SVUnit. They provide their own UVM reporter and redefine `uvm_error to call that instead. I was hoping that UVM already had a more built-in mechanism for intercepting messages. If so, I could simply put the intercepted messages in a queue, verify that the queue contains the messages I expect and then pass/fail the test accordingly. I have to dig deeper and learn more but I was hoping that there would be a UVM action I can use or maybe uvm_report_catcher which by the name of it sounds related. Maybe these concepts can't be used for what I'm trying to do?
  4. What is the preferred way to verify that a verification component calls uvm_error when it's supposed to without that error causing an error for my test? I know about SVUnit and its mocking capabilities but is it a way to do this within UVM?
  5. sas73

    Log File Parsing

    Thanks @dave_59. I did a quick test with the commercial simulators available at EDA playground with the following error scenarios: 1. Assert with $error 2. Null object dereferencing Riviera-PRO would do a normal exit in both these scenarios, Cadence has a non-zero return code for both and Synopsis return non-zero for the null object dereferencing but not for the assert. I didn't check if there are option flags that would change this behavior but it seems that there are different opinions on how the return code should be used. Personally I would fail a test with a non-zero exit regardless of simulator strategy and log file contents. I would also prefer that the tools would use the return code for the errors they know about, at least as an option. Let's say I have a smaller project just using SystemVerilog with $error or VHDL asserts with error severity. The return code would give me pass/fail status if the assertions fail or if there is another problem like null object dereferencing . If it passed I don't care about the logs and if it failed they are small enough to be read manually. If I have a project using less specific error mechanisms like Verilog $display I would need parsing but the scope of parsing is reduced. If I have many long log files I may need scripting to mine them for the interesting events but in that case I rather have more machine readable formats that is well supported by scripting languages. XML or JSON for example. It would make the scripting easier and less error prone.
  6. sas73

    Log File Parsing

    @David BlackWhat would you say is standard praxis for parsing logs to figure out pass/fail status? Find standard patterns for UVM errors + find simulator specific patterns for other errors + make sure there is a UVM report to catch silent errors stopping the simulation? Do people ever look at the return code? Testing at EDA Playground I see that some simulators return a non-zero code for some, but not all, errors. Why isn't this used more? Keeps me from knowing simulator specific error messages and makes the script more portable.
  7. I'm trying to find existing libraries of reusable assert macros that uses UVM messaging. For example checking equality and if it fails it would generate a message of expected and received values using uvm_error. What are my options?
  8. Thanks David. It sounds like no such tests are available. Open source projects in general are not always good at providing their test suites but I find it a bit odd that on open source library for verification doesn't provide the test suites showing how the library itself is verified. It would be easier for people to suggest improvements if they can verify whether or not such a modification breaks something else.
  9. sas73

    Log File Parsing

    Thanks David! I'll look into that.
  10. Hi, Are there any openly available (template) scripts to parse log files to find non-UVM error messages? Thanks
  11. Hi, I just downloaded the UVM library but I couldn't find any tests verifying its functionality. Are such tests available? Also, is the git repository from which the library was released open? Thanks
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