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taog

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  1. OK, I see, thanks. So the guideline is using TLM like way(Pure function call, no SystemC schedule related) to carry signals when using quantum, right?
  2. For solution 2 "if your CPU writes into the register of your interrupt controller via TLM it carries the delay which is essentially the offset of the CPU local time to the SystemC kernel time. If you here just break the quantum and call a wait() so that the SystemC kernel can sync up and the signal change propagates", what if this interrupt is cleared by other models instead of my CPU model? How my CPU model can sense the external signal change(Interrupt value change) immediately?
  3. It looks like we need to sync with SystemC kernel once CPU access other models in the system. Anyway, we must balance simulation performance and correct model behavior.
  4. Dear experts, I'm developing an ISS SystemC wrapper for a processor. In the SystemC wrapper, I decided to use quantum keeper to improve simulation performance. But, I found some issues when handling external interrupt. An external interrupt controller model is connect with my processor model by using some "sc_signal". When executing interrupt handler, SW need to clear interrupt by write some register in the external interrupt controller. But, my model used quantum keeper, it always need to execute enough instructions to reach quantum without sync with SystemC kernel. So, of cause, it do not know that the interrupt has already been cleared until it reached quantum. It always entered interrupt handler multi times. Who can tell me some solutions???
  5. I want to create a SystemC class as a derivative of another SystemC class like below: struct A : public sc_module { ... tlm_utils::multi_passthrough_target_socket<A, 32, tlm::tlm_base_protocol_types, 0, sc_core::SC_ZERO_OR_MORE_BOUND> tsocket; ... }; struct B : public A { ... }; struct C : public sc_module { ... tlm_utils::multi_passthrough_initiator_socket<C, 32, tlm::tlm_base_protocol_types, 0, sc_core::SC_ZERO_OR_MORE_BOUND> isocket; ... }; Then I need to bind B to C B b; C c; C->isocket.bind(b->tsocket); But, I will get some runtime error like below: Error: (E120) sc_export instance has no interface: B.tsocket In file: /home/tools/vcs/mx-2017.12-1/include/systemc231/sysc/communication/sc_export.h:162 Does SystemC do not support such a use case? Or I only need to do some “cast” to bind this socket? I'm not sure if it will bring some side-effect.
  6. I'm really agree with you. I think it's because of we do not familiar with SystemC implement, and not sure if it would bring us some side-effects or restrictions when we apply SystemC in all our models. What we need is that we can reuse our models under different simulators with as less effort as possible.
  7. Because in my project, we need to use our models in a non-SystemC simulator(C++ based). We do not want to use SystemC scheduler. We only want to use TLM-2.0 to unify function calls between our modules. Another thing is that we do not want to link SystemC library because SystemC seems have some global objects which may not easy to support checkpointing.
  8. It seems I can not use tlm2 socket like simple_initiator_socket/simple_target_socket in a pure C++ class which do not inherent from sc_module. Is TLM2 socket tight coupling with sc_module? Can I decouple this relationship?
  9. Ok, I see. Another question, can I use TLM-2.0 infrastructure like initiator socket/target socket/generic payload/socket bind/register b_transport function without trigger systemc kernel by using sc_start in my pure C++ simulation enviroment?
  10. Get it, thank you, maehne.
  11. I've tried link against the static library libsystemc.a, I got error below: /home/taog/tools/systemc-2.3.1/lib-linux64//libsystemc.a(sc_main_main.o): In function `sc_elab_and_sim': /home/taog/tools_src/systemc-2.3.1a/objdir/src/sysc/kernel/../../../../src/sysc/kernel/sc_main_main.cpp:84: undefined reference to `sc_main' I need to pack a library based on SystemC, adding a empty sc_main in a library is weld.
  12. Hi all, in my opinion, TLM-2.0 defines the communication protocol between modules. Can I just use TLM-2.0 generic payload/b_transport without SystemC, just in a pure C++ enviroment??? When I compiled my C++ program which have included TLM2 headers, it give me some errors, like below: undefined reference to `sc_core::sc_port_base::add_static_event(sc_core::sc_method_process*, sc_core::sc_event const&) const' Must I link SystemC library to use TLM-2.0? i'm using SystemC-2.3.0
  13. Hi all, I'm not familiar with SystemC source code. I'm debugging a segment fault issue inside SystemC. The call stack is like below: #0 0x000000000048124e in sc_core::sc_inout<bool>::end_of_elaboration() () #1 0x0000000000473d8e in sc_core::sc_port_base::elaboration_done() () #2 0x0000000000474ab3 in sc_core::sc_port_registry::elaboration_done() () #3 0x00000000004e1e0c in sc_core::sc_simcontext::elaborate() () #4 0x00000000004e3d1d in sc_core::sc_simcontext::initialize(bool, bool) () #5 0x00000000004e3e04 in sc_core::sc_simcontext::initialize(bool) () #6 0x00000000004e3e26 in sc_core::sc_simcontext::simulate(sc_core::sc_time const&) () #7 0x00000000004e4022 in sc_core::sc_start(sc_core::sc_time const&, sc_core::sc_starvation_policy) () In src/sysc/communication/sc_port.cpp, I found void sc_port_base::elaboration_done() { assert( m_bind_info != 0 && m_bind_info->complete ); delete m_bind_info; m_bind_info = 0; sc_module* parent = static_cast<sc_module*>( get_parent_object() ); sc_object::hierarchy_scope scope( parent ); end_of_elaboration(); } // called by elaboration_done (does nothing) void sc_port_base::end_of_elaboration() {} Why we call end_of_elaboration() here and why we come to sc_core::sc_inout<bool>::end_of_elaboration()? Maybe the call stack is not correct.
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