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Everything posted by Bhargav

  1. Hi, I am working on IPXACTS -RTL representation. I have seen the following in one of my IPXACTS, where parameters are defined. I have a question regarding this value representation in this above IPXACT. Is this valid as per the standards? And does this mean, in RTL, the following: parameter [0:0] RD_ADDR_INI_PIPE_STAGE [NUM_CORE_INI-1:0] = '{1,1}
  2. Bhargav

    Parameter value definition in IPXACTs

    Thanks Erwin. Best Regards, Bhargav Kandru.
  3. Bhargav

    Glue Logics in IPXACT

    Okay Erwin. Thanks for the info. Best Regards, Bhargav Kandru.
  4. Bhargav

    Glue Logics in IPXACT

    Hi, I have a question in how glue logics between two or more ports get represented in IPXACT. Lets say there is an ADHOC Connection between, PORT A of instance A and PORT B of instance B, in such a way that, PORTB is connected as 32'habcd ^ PORTA Like, Instance A: output port A Instance B: input port B Now, on Top file, In SV , I have following glue logic. module Top module A instance A( .A(A) ) module B instance B( .B(32'habcd ^ A) //32'habcd XOR with A ) endmodule Now, in adHoc connection,we genrally, represent two connections with just internalportreferences. How does such glue logics get represented? Thanks in advance.
  5. HI, What is the purpose of the element, ARRAYS present in component IPXACT definition. In the above image, the port has name: defining physical port name, direction: wire direction, vectors: msb and lsb of the port. What I don't understand is the purpose of arrays here. What it implies? Is it kind of multi dimensional port definition. If so, don't we already have indices, index defining them? Thanks in advance, Bhargav K
  6. Hi Erwin, Thanks for that. So basically, in RTL, it is indicating, some port like: "input TAR_PRI_RD [32:0][5:0]" I want to implement a multidimensional ports, or I have an array of array of ports in my verilog files, how do the get reflected in my IPXACT? Is the below one proper if I want to implement input [32:0][3:0][7:0][4:0] port in my RTL <ipxact:port> <ipxact:name>port</ipxact:name> <ipxact:wire> <ipxact:direction>in</ipxact:direction> <ipxact:vectors> <ipxact:vector> <ipxact:left>32</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:vector> </ipxact:vectors> </ipxact:wire> <ipxact:arrays> <ipxact:array> <ipxact:left>3</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:array> <ipxact:array> <ipxact:left>7</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:array> <ipxact:array> <ipxact:left>4</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:array> </ipxact:arrays> </ipxact:port> Thanks in advance, Bhargav
  7. Previous versions of IPXACT has attributes, 'left' and 'right' inside internalPortReference element of adHocConnection in design IPXACT as shown in the following 4 lines of xml. <spirit:adHocConnection> <spirit:name>....</spirit:name> <spirit:internalPortReference spirit:ComponentRef = "..." spirit:PortRef=".." spirit:left="..." spirit:right="...."/> </spirit:adHocConnection> These attributes basically say that which vector range of port from one component is mapped to another (I assume) However, the same IPXACT with latest schema, while validation gives schema error stating, attribute right/left is not allowed. Even the latest xsd files available with accellera doesn't define these attributes.There must be some means how currently, these multibit adHocConnections are mapped between two components inside an IPXACT-design. What could be the solution for this?
  8. That was very useful for me Erwin. Thank You. Will there be any significance, if I connect two unequal length ports under adHocConnection. Suppose, port A[3:0], connected to port B[7:0]. Just as below: <ipxact:adHocConnection> <ipxact:name>adhoc1</ipxact:name> <ipxact:portReferences> <ipxact:internalPortReference componentRef="cA" portRef="A"> <ipxact:partSelect> <ipxact:range> <ipxact:left>3</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:range>  </ipxact:partSelect> </ipxact:internalPortReference>  <ipxact:internalPortReference componentRef="cB" portRef="B"> <ipxact:partSelect> <ipxact:range> <ipxact:left>7</ipxact:left> <ipxact:right>0</ipxact:right> </ipxact:range> </ipxact:partSelect> </ipxact:internalPortReference> </ipxact:portReferences>  </ipxact:adHocConnection> In this case, what is the IPXACT exactly stating? A[3:0] connected to B[7:4], with B[3:0] left unconnected or the other way? or this IPXACT description is entirely invalid as incorrect length vectors are tied up? Best Regards, Bhargav K
  9. Hi Erwin, Thanks for that. I tried the above mentioned solution and its working. I have a question regarding connectivity of multidimensional port range. I tried to implement multidimensional ports like below attached image in my xml: It is giving this error while validation: "Element range is not expected". Must be because, range element max bound is only one. If that is the case, how to implement the following case: I have a port A from component1 like this: A[2:0][2:0] and port B of component2: B[5:3][6:4] and are supposed to be connected. Now, how will I regenerate this in IPXACT? If I am using, "indices" element, with two indexes, each for each dimension, still I will be able to give range definition only once. I mean, I can give connectivity information for only one dimension of A and B. What about the range information for the second dimension? Best regards, Bhargav Kandru.