Jump to content


  • Content Count

  • Joined

  • Last visited

About Veeraraju

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Iam seeing issue with mux output from clocking block(Inputs(a,b,sel) are delayed correctly by 1ns where as outputs is in sync with clk). DUT definition: module mux(a,b,sel,clk,out); input [4:0] a; input [4:0] b; input clk; input sel; output [4:0] out; reg [4:0] out_temp; always @(posedge clk) begin if(sel==0) out_temp <=a; if(sel==1) out_temp <=b; end assign out =out_temp; endmodule Interface definition: interface mux_if(input clk); logic [4:0] a; logic [4:0] b; logic sel; logic [4:0] out; clocking mux_cb @(posedge clk); default input #1ns output #1ns; input out; output a,b; output sel ; endclocking endinterface In TB iam instantiating DUT as mux mux_inst(.clk(mux_if1.clk), .a(mux_if1.a), .b(mux_if1.b), .sel(mux_if1.sel), .out(mux_if1.out) );