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Khushi

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  1. Thanks Philip Can you tell me for a scenario when payload data length is 16 bytes the n what value of DATAWORD I should use when using _generic endianness conversion function. For my specific case, I do not have the byte enable constraints. Can I use my function to convert the payload data from BE to LE on bus width boundary before calling b_transport and use the opposite one when b_transport call returns. For example, If I have the following data (16 bytes) char *data = "ABCDEFGHIJKLMNOP", then my function convert it to "DCBAHGFELKJIPONM" for a socket of 32bit. Can we do it ? Thanks
  2. Hi , I am looking at endianness conversion functions in 1666-2011.pdf @492. I have couple of related questions 1. What is the template parameter DATAWORD signifies in these functions. Why it is needed when we pass the socket size explicitly 2. There are following functions for to_hostendian_ inline void tlm_to_hostendian_generic(tlm_generic_payload *, unsigned int ); inline void tlm_to_hostendian_word(tlm_generic_payload *, unsigned int); inline void tlm_to_hostendian_aligned(tlm_generic_payload *, unsigned int); inline void tlm_to_hostendian_single(tlm_generic_payload *, unsigned int); Which function we should use ? What is the meaning of _generic, _word, _aligned and _single in these functions Same for _from_hostendian functions. Thanks in advance for your kind help -- Khushi
  3. Hi Jrefice Thanks for the guidance. Can you elaborate a little more. I mean what to clone and where. I can try accordingly. Thanks
  4. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  5. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  6. Hi Folks I have a scenario where a DUT register value changes when IP reaches a certain state. This change in register value is done internally in the RTL implementation of the DUT, it is not through any bus transaction. In such cases how I update the corresponding register value (mirror or desired) in its UVM register model ? Thanks in Advance Thanks Khushi
  7. Hi In UVM_ML, how to connect the following ports (from SystemC-TLM model to rest of the UVM verification env) - sc_in<int> - sc_out<bool> -sc_port<my_if<T1>> - sc_export<my_if<T1>> Thanks
  8. Hi Guys I am trying to use uvm_reg_hw_reset_seq built in sequence but it seems it generates all address (e.g. 0x0,0x1,0x2,0x3,0x4,...) but as the registers are 32 bit, I expect 0x0,0x4,0x8 etc How I can control this ? Thanks
  9. Hi Guys I have a scenario where I have an target module in SystemC-TLM2 with a tlm_target_socket. I developed a UVM based verification env to verify that SystemC-TLM2 model. In UVM test bench I have an initiator module which calls b_transport with some payload and in SystemC-TLM2 target side I have the implementation of b_transport. I can see the the payload reaching on systemc side but when I change the payload (e.g. data or address) in b_transport implementation, the changes are not reflected on UVM initiator after the b_transport call returns. I am not able to understand what is going wrong. Any help or guidance will be highly appreciated, I am using Cadence UVM-ML for this. Thanks Khushi
  10. Hi Guys I am very new to UVM and trying to play around with a small example(see below). In this example what I am observing that the following sequence(at each posedge) - first monitor run_phase is executed - rtl is executed - driver is executed due to this, I get the following output UVM_INFO example.sv(112) @ 10: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x0 in=x UVM_INFO example.sv(42) @ 10: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xd, out = 0x0 UVM_INFO example.sv(112) @ 30: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x0 in=d UVM_INFO example.sv(42) @ 30: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xa, out = 0x2 UVM_INFO example.sv(112) @ 50: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x1a in=a UVM_INFO example.sv(42) @ 50: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0x4, out = 0x6 UVM_INFO example.sv(112) @ 70: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x14 in=4 UVM_INFO example.sv(42) @ 70: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xc, out = 0xc But I want the following order(at each posedge) - driver run_phase - rtl - monitor run phase so that monitor display correct output. How I can achieve this. Or is there some other way to get the correct output. Here is the complete code import uvm_pkg::*; `include "uvm_macros.svh" module dut( input clk, input [3:0] in, output reg [4:0] out ); always @ (posedge clk) begin $display("in=%h",in); out <= 2*in; end endmodule interface dut_if (input clk); logic [3:0] in; logic [4:0] out; endinterface module dut_wrapper(dut_if _if); dut dut0(.clk (_if.clk), .in (_if.in), .out (_if.out)); endmodule class data_item extends uvm_sequence_item; `uvm_object_utils(data_item) rand bit [3:0] in; rand bit [4:0] out; constraint c_in {in >=0;in<=15;} function new (string name = ""); super.new(name); endfunction virtual function void display (); `uvm_info (get_type_name (), $sformatf ("in = 0x%0h, out = 0x%0h", in,out), UVM_LOW); endfunction endclass class data_sequence extends uvm_sequence; `uvm_object_utils(data_sequence) data_item m_data_item; function new (string name="data_sequence"); super.new(name); endfunction virtual task body(); m_data_item = data_item::type_id::create("m_data_item"); repeat (4) begin start_item(m_data_item); assert(m_data_item.randomize()) finish_item(m_data_item); end endtask endclass class driver extends uvm_driver#(data_item); `uvm_component_utils(driver) data_item m_data_item; virtual dut_if m_dut_if; function new(string name,uvm_component parent); super.new(name,parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "m_dut_if", m_dut_if)); endfunction task run_phase(uvm_phase phase); forever begin @(posedge m_dut_if.clk); seq_item_port.get_next_item (m_data_item); m_dut_if.in = m_data_item.in; m_data_item.display(); seq_item_port.item_done(); end endtask endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual dut_if m_dut_if; uvm_analysis_port #(data_item) item_collected_port; data_item m_data_item; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase (uvm_phase phase); super.build_phase (phase); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "m_dut_if", m_dut_if)); endfunction task run_phase(uvm_phase phase); super.run_phase(phase); m_data_item = data_item::type_id::create ("m_data_item", this); forever @(posedge m_dut_if.clk) begin m_data_item.out = m_dut_if.out; `uvm_info (get_type_name (), $sformatf ("out = 0x%0h", m_data_item.out), UVM_LOW); //item_collected_port.write (m_data_item); end endtask endclass class agent extends uvm_agent; `uvm_component_utils(agent) driver m_driver; data_sequence m_data_sequence; uvm_sequencer#(data_item) m_data_sequencer; monitor m_monitor; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_driver = driver::type_id::create("m_driver",this); m_data_sequence = data_sequence::type_id::create("m_data_sequence",this); m_data_sequencer = uvm_sequencer#(data_item)::type_id::create("m_data_sequencer",this); m_monitor = monitor::type_id::create ("m_monitor", this); endfunction virtual function void connect_phase (uvm_phase phase); super.connect_phase (phase); m_driver.seq_item_port.connect (m_data_sequencer.seq_item_export); endfunction endclass class env extends uvm_env; `uvm_component_utils(env) agent m_agent; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_agent = agent::type_id::create("m_agent",this); endfunction endclass class my_test extends uvm_test; `uvm_component_utils(my_test) env m_env; virtual dut_if m_dut_if; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_env = env::type_id::create("m_env",this); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "dut_if", m_dut_if)); uvm_config_db #(virtual dut_if) :: set (this, "*", "m_dut_if", m_dut_if); endfunction virtual function void end_of_elaboration_phase (uvm_phase phase); uvm_top.print_topology (); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); m_env.m_agent.m_data_sequence.start(m_env.m_agent.m_data_sequencer); phase.drop_objection(this); endtask endclass module top; bit clk; always #10 clk <= ~clk; dut_if m_dut_if(clk); dut_wrapper m_dut_wrapper(._if(m_dut_if)); initial begin uvm_config_db #(virtual dut_if)::set (null, "uvm_test_top", "dut_if", m_dut_if); run_test("my_test"); end endmodule
  11. In UVM verification env, do we need to use two monitor if I want to sample the input (to DUT)and output(from DUT) and compare them in scoreboard. In this case do I need to use two monitor, one on input and other on output ? Can a single monitor does the same job ? I tried but what I see by the time output arrives the input changes(for next set of inputs) Thanks
  12. Hi Guys I am trying to put in place a generic UVM verification env for TLM IPs. For RTL IPs we usually define the interface like(for simple adder) interface dut_if (input clk); logic [3:0] in1; logic [3:0] in2; logic [4:0] out; endinterface What the interface definition look like for TLM2 interfaces (for example if DUT has a target socket) Thanks Khushi
  13. Hello Guys I have a scenario where I have an initiator module on SystemC side and target module on UVL side. From initiator side, I call b_transport with some payload and in target side the data field is modified. What I am seeing that when b_transport returns on initiator module, the changes in data field is not reflected. On SystemC side, I have a thread with following function void run(){ int i = 4; while(i--){ cout<<" in run........"<<endl; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(100, SC_NS); trans->set_command(tlm::TLM_WRITE_COMMAND); uint64_t addr = 0x0; uint8_t data = 0xa5; uint32_t length = 1; trans->set_address(addr); trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data)); trans->set_data_length(length); trans->set_streaming_width(length); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); initiator_socket->b_transport(*trans,delay); cout<<"Result : 0xa5 vs 0x"<<hex<<+data<<endl; wait(delay); } } On UVM target side, my b_transport implementation is as follows task b_transport(uvm_tlm_generic_payload gp, uvm_tlm_time delay); byte unsigned data[]; gp.get_data(data); `uvm_info("INFO", $sformatf("entering b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); data[0] = ~data[0]; gp.set_data(data); `uvm_info("INFO", $sformatf("exiting b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); endtask and the output I am getting is UVM_INFO @ 0: reporter [RNTST] Running test SV:sv_top set by +UVM_TESTNAME... in run........ UVM_INFO sv_target.sv(31) @ 0: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 0: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 100000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 100000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 200000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 200000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 300000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 300000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 It seems that on UVM side the data field is updated well but on TLM side it is not reflected. Can you help me to understand what is going wrong here ? Thanks Khushi
  14. With the following code, import uvm_pkg::*; `include "uvm_macros.svh" class seq_data extends uvm_sequence_item; `uvm_object_utils(seq_data) rand bit [7:0] addr; rand bit [7:0] data; constraint c_addr {addr >=1000;addr<2000;} constraint c_data {data >=0000;data<=4000;} function new (string name = "",uvm_component parent=null); super.new(name); endfunction virtual function void display (); `uvm_info (get_type_name (), $sformatf ("addr = 0x%0h, data = 0x%0h", addr, data), UVM_LOW); endfunction endclass class my_test extends uvm_test; `uvm_component_utils(my_test) seq_data my_data; function new(string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); my_data = seq_data::type_id::create("my_data",this); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); repeat(4) begin #10; assert(my_data.randomize()); my_data.display(); end phase.drop_objection(this); endtask endclass module top; initial begin run_test("my_test"); end endmodule I am getting the following error xmsim: *E,ASRTST (./example.sv,38): (time 30 NS) Assertion worklib.$unit_0x762d41ec::my_test::run_phase.__assert_1 has failed UVM_INFO example.sv(17) @ 30: reporter@@my_data [seq_data] addr = 0x0, data = 0x0 assert(my_data.randomize()); | xmsim: *W,SVRNDF (./example.sv,38|32): The randomize method call failed. The unique id of the failed randomize call is 3. Observed simulation time : 40 NS + 0 xmsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints: constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) xmsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints: rand variables: addr [./example.sv, 6] I am not seeing any constraint with the following expression constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) Can someone help me to understand what is going wrong here ? Thanks Khushi
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