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Khushi

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  1. hi guys In TLM2 the tlm::tlm_global_quantum class is a singleton so it does not allow us to have different global quantum for different instances. Is it a way to have different instances have different global quantums ? For example instance1 sync at each 500 ns and instance 2 sync at each 1000 ns ? Thanks Khushi
  2. Hello All I have a confusion regarding the BUSWIDTH template with TLM2 sockets. In TLM sockets e.g. tlm_initiator_socket/simple_target_socket, why we have BUSWIDTH template and what is the need for this. If I want to transfer 256 bit data from an initiator (with tlm_initiator_socket port on it) to a target (with tlm_target_socket port on it), I can do it in one go by setting the data length and data pointer payload fields appropriately irrespective of the BUSWIDTH template. Whether I use BUSWIDTH 1 or 8 or 16 or 32 and so on, I can still call the b_transport and transfer the data in one go. So what is the significance of this BUSWIDTH template parameter. Where it is actually makes a difference. Thanks Khushi
  3. Hi How can I count the number of SC_THREAD/SC_METHOD in a given simulation of a SystemC platform ? Is it possible ? Thanks Khushi
  4. Khushi

    Array of ports

    Thanks Eyck. Appreciated your quick help. Thanks again, Khushi
  5. Hi Guys I have a scenario where I have to connect sc_in<uint32_t> in_port to an sc_out<bool> out[32] out_ports. i.e. the xth bit in in_port need to be connected to out[x] Is there a way to connect these ? Thanks Khushi
  6. Many thanks Roman. You suggestion works. Thanks again - Khushi
  7. Hi Guys Is it possible to connect sc_in<bool> hierarchically to another sc_in<bool> (same for sc_out<bool> as well) ? I tried the attached exmples ex1.cpp Error: (E109) complete binding failed: port not bound: port 'target.target_h.in' (sc_in) ex2.cpp : Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'target.in_h' (sc_in) Can you please help me ? Thanks Khushi ex1.cpp ex2.cpp
  8. Hi I found it is overloaded in sc_module class. Sorry for the inconvenience Thanks
  9. Hi I am looking into the risc_cpu example in systemc package and I am not able to understand the following(at line 321) exec IEU("EXEC_BLOCK"); IEU << reset << decode_valid << alu_op << negate << add1 << shift_sel << src_A << src_B << forward_A << forward_B << alu_src << c << v << z << dout << out_valid << destout << clk; It seems it is related to binding. If yes ,can you tell me where the << is overloaded to have the bindings. Thanks Khushi
  10. Thanks Philip Can you tell me for a scenario when payload data length is 16 bytes the n what value of DATAWORD I should use when using _generic endianness conversion function. For my specific case, I do not have the byte enable constraints. Can I use my function to convert the payload data from BE to LE on bus width boundary before calling b_transport and use the opposite one when b_transport call returns. For example, If I have the following data (16 bytes) char *data = "ABCDEFGHIJKLMNOP", then my function convert it to "DCBAHGFELKJIPONM" for a socket of 32bit. Can we do it ? Thanks
  11. Hi , I am looking at endianness conversion functions in 1666-2011.pdf @492. I have couple of related questions 1. What is the template parameter DATAWORD signifies in these functions. Why it is needed when we pass the socket size explicitly 2. There are following functions for to_hostendian_ inline void tlm_to_hostendian_generic(tlm_generic_payload *, unsigned int ); inline void tlm_to_hostendian_word(tlm_generic_payload *, unsigned int); inline void tlm_to_hostendian_aligned(tlm_generic_payload *, unsigned int); inline void tlm_to_hostendian_single(tlm_generic_payload *, unsigned int); Which function we should use ? What is the meaning of _generic, _word, _aligned and _single in these functions Same for _from_hostendian functions. Thanks in advance for your kind help -- Khushi
  12. Hi Jrefice Thanks for the guidance. Can you elaborate a little more. I mean what to clone and where. I can try accordingly. Thanks
  13. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  14. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  15. Hi Folks I have a scenario where a DUT register value changes when IP reaches a certain state. This change in register value is done internally in the RTL implementation of the DUT, it is not through any bus transaction. In such cases how I update the corresponding register value (mirror or desired) in its UVM register model ? Thanks in Advance Thanks Khushi
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