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veeresh k

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  1. veeresh k

    clock generation in system c

    Ok Eyck. Thanx for d reply . 🙂 It wont be clear untill n unless,i do more n more examples on my own. To certain extent, u guys made me clear of few topics. Thank you once again.
  2. veeresh k

    clock generation in system c

    Hey ameya, Thanx for the reply. 🙂 I have gone through documentation,but am not getting it completely. By seeing the suggested api documentation from u,i am assuming that we will have a time period of 1ps along with 0.5 dutycycle by default and we are changing a bit of start value of clock by using sc_start(1,SC_NS) .We just got to declare it and mention it in trace file n we will get the waveform,ryt? As u can see in below waveform,i know the reason for reset and enable changes,but the clock waveform reason i dint get. N how can i change the clock waveform.Is it done by this sc_clock testclk("testclk",2,SC_NS,0.5,1,SC_NS). Note:-In test clock i am just randomly taking the no. .
  3. veeresh k

    clock generation in system c

    Hi, I have came across this counter example from other website. Can u please tell me ,where have we intitialised the main clock. I know the default time period is 1ps,but i am not getting the start of the clock is from which point. I am not knowing the reason for its generation in waveform viewer. Thank you. Below is the code: #include "systemc.h" #include "design.cpp" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> reset; sc_signal<bool> enable; sc_signal<sc_uint<4> > counter_out; int i = 0; // Connect the DUT first_counter counter("COUNTER"); counter.clock(clock); counter.reset(reset); counter.enable(enable); counter.counter_out(counter_out); sc_start(1, SC_NS); // Open VCD file sc_trace_file *wf = sc_create_vcd_trace_file("counter"); // Dump the desired signals sc_trace(wf, clock, "clock"); sc_trace(wf, reset, "reset"); sc_trace(wf, enable, "enable"); sc_trace(wf, counter_out, "count"); // Initialize all variables reset = 0; // initial value of reset enable = 0; // initial value of enable for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 1; // Assert the reset cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl; for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 0; // De-assert the reset cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl; for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl; enable = 1; // Assert enable for (i=0;i<20;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl; enable = 0; // De-assert enable cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl; sc_close_vcd_trace_file(wf); return 0;// Terminate simulation }
  4. veeresh k

    system c beginner

    Seriously david, Thanks a ton. 🙂 Thank you for letting me know the aspects which i need to cover. Presently i am working with counter and flip flop examples,which are good enough to be carried with intermediate c++ knowledge i think. But the moment, when i will be starting with prim and hierarchial channels, i believe i will be needing the advanced topics. Please ,correct me if i am wrong.
  5. veeresh k

    system c beginner

    As of now,i am familiar with oops concepts and have an intermediate level c++ knowledge. Is it enough or do i need to get much more knowledge regarding c++. Because everytime,i am starting afresh and ending up with more and more doubts. Thank you.
  6. veeresh k

    system c beginner

    Hi, I am new to system c. I am trying to learn it step by step,but getting messed up with arrival of every new topic. Any suggestions for good book ? Currently i am studying system c primer by J.Bhasker. Please, help me out. Thank you.
  7. Can someone please explain with a simple example of up/down counter?
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