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ddc1234

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  1. I am working on a project where we have multiple independent IP designs which i'll call "cores". Each core has its own set of registers accessed through a single register interface bus. We also have subsystems which have some top level registers and instantiate multiple cores (sometimes multiple instances of the same core). There is still a single register interface bus which is used to access all of the cores (each is instantiated with an base address offset such that none of there addresses overlap with other cores). Each Core has a corresponding IP-Xact component description which defines the basic memoryMaps for that core. Basically the XML file consists of only the VLNV and the memoryMaps section. So far this has worked fine for our needs at the core level. However I'm not sure how to define the overall memoryMap of a subsystem consisting of multiple cores. My understanding is that I need to make a component for the subsystem which defines its own top level registers in its memoryMaps section, however I don't see how I can reference the maps of other components within the subsystems' memory map. My question would be: How can I define the memoryMap of the subsystem as a whole without having to literally copy the memoryMap of a core into the memoryMap of the subsystem. Is there a fundemental flaw in the way I am thinking about this?
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