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Mengyu

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  1. Thanks Roman, now this concept is clear for me.
  2. Thanks Roman, a similar question: When exactly the elaboration and simulation process starts in SystemC? From my understanding, the elaboration starts when I instantiate the top module in sc_main and simulation starts when I call "sc_start" function. I failed to find the answer in SystemC IEEE_1666 stardard reference manual, could you please give me some hints?
  3. Hi Roman, Thanks for your reply. Now I'm little confused by the elaboration and simulation process. Actually I'm trying to initialize the sc_vector with a value that is calculated during simulation-time, is this allowed in SystemC? From your reply, it seems that the initialization of sc_vector can only happen at elaboration process.
  4. Hi, I have a question about how to use the callback before_end_of_elaboration. For example, I have a top module and a submodule. The submodule takes an input "a" and I would like to use this input to initialize an vector in its constructor. SC_MODULE(sub_module) { sc_in<sc_uint<10> > a; sc_vector<sc_signal<sc_uint<4> > > b; SC_CTOR(sub_module) { b.init(a); } }; SC_MODULE(top) { sub_module *sub_module_nm; SC_CTOR(top) { sub_module_nm = new sub_module("sub_module_nm"); sub_module_nm->a(...); } } As you can see, I perforemed the port binding in the top module(which is what I usually do). But from my understanding, I can not access to input "a" unless I perform the port binding in the before_end_of_elaboration() callback of submodule. And my question is how to do the port binding in the submodule rather than at top level so I could perform some initialization after the port has been bound. Thanks, Mengyu
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