Jump to content

jatin jatin

Members
  • Content count

    7
  • Joined

  • Last visited

About jatin jatin

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. jatin jatin

    It can have two constructors in a SC_MODULE?

    @apfitch Hello Sir, Sir can you please tell me how would i make objects and how would i pass arguments in these constructors. or if you could provide me any link where i can read about parameterized constructor of systemc. regards, jatin
  2. jatin jatin

    clock problem

    @David Black Sir, i'm waiting for your reply. regards, jatin
  3. jatin jatin

    clock problem

    Hello Sir, I am a noob i have just started learning systemC(It's been just 3 weeks) and i did not know about uint8_t, now i will try it and explore it. Sir please check the attached file for specification. also can you please give me a simple example in which time period has passed through constructor actually i want to see the syntax. In my design there is one more problem : "whenever i enable my constructor after disabling, it gives wrong output".!! regards, jatin up_timer.pdf
  4. jatin jatin

    clock problem

    Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin
  5. jatin jatin

    how to implement delay in systemC?

    Hi Roman, I am glad that you respond. Here is a code of an adder i implemented. Here the output is updating after 2ns of input change. i.e. i implemented the intra assignment delay of 2 ns using sc_event and SC_METHOD(). This code works fine. ***NOW, SOMEONE WHO KNOWS SYSTEMC VERY WELL WANTS ME TO IMPLEMENT THE SAME USING SC_THREAD AND WITHOUT USING SC_EVENT()*** so it would be great if you could suggest somthing. #include<systemc.h> sc_int<32> out; sc_event e; // design module// SC_MODULE(adder) { sc_in< sc_int<16> > a; sc_in< sc_int<16> > b; sc_out< sc_int<32> > outp; void toggle() { out= a.read() + b.read(); e.notify(2,SC_NS); } void add() { outp.write(out); } void show() { cout<<"||sum @ "<<sc_time_stamp()<<"\t:\t\t\t"<<outp<<endl; } SC_CTOR(adder) { SC_METHOD(add); sensitive << out; dont_initialize(); SC_METHOD(toggle); sensitive << a << b; dont_initialize(); SC_METHOD(show); sensitive <<outp; dont_initialize(); } }; // test bench // SC_MODULE(tb) { sc_out< sc_int<16> > a,b; void stimulus() { a.write(0); b.write(0); wait(5,SC_NS); a.write(5); b.write(0); wait(2,SC_NS); a.write(5); b.write(5); wait(8,SC_NS); a.write(7); b.write(8); wait(5,SC_NS); sc_stop(); } void show() { cout<<"inputs @"<<sc_time_stamp()<<" :\t"<<a<<"\t|\t"<<b<<"\t"; } SC_CTOR(tb) { SC_THREAD(stimulus); SC_METHOD(show); sensitive << a<< b; } }; int sc_main(int argc, char* argv[]) { tb tb0("tbinst"); adder ad("adinst"); sc_signal< sc_int<16> > a_sig, b_sig; sc_signal< sc_int<32> > outp_sig; tb0.a(a_sig); tb0.b(b_sig); ad.a(a_sig); ad.b(b_sig); ad.outp(outp_sig); cout<<"a \t:\tb \n"; sc_start(); return 0; } regards jatin
  6. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  7. jatin jatin

    How to model a delay line in SystemC

    Hi Roman Popov, is there any way to implement the intra assignment delay without using sc_event()? regards jatin
×