Jump to content

Shobhana soni

Members
  • Content count

    4
  • Joined

  • Last visited

About Shobhana soni

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Shobhana soni

    Uvm

    In UVM phases provide synchroniztion between components but in systemverilog it's not like that what makes it difficult for sv as they are not having phases . Thanks
  2. Shobhana soni

    Uvm

    In UVM phases phases provide synchroniztion between components but in systemverilog it's not like that what makes it difficult for sv as they are not having phases
  3. Shobhana soni

    Constraints

    How to write a constraint for random variable which is divisible by 7 && 17
×