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Shobhana soni

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  1. Uvm

    In UVM phases provide synchroniztion between components but in systemverilog it's not like that what makes it difficult for sv as they are not having phases . Thanks
  2. Uvm

    In UVM phases phases provide synchroniztion between components but in systemverilog it's not like that what makes it difficult for sv as they are not having phases
  3. Constraints

    How to write a constraint for random variable which is divisible by 7 && 17
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