cooltoad posted a topic in UVM SystemVerilog DiscussionsHello, I am developing a verification environment for a DUT that has cache memory in it. I would like to model that memory in my environment and make it accessible to various components at different levels of hierarchy. What is the best way to add "hooks" for the same? This is what my env looks like. class top_env extends ovm_env; `ovm_component_utils(top_env) mem_model mem_model_h; scoreboard scoreboard_h; checker checker_h; endclass I want the mem_model to be accessible to all the components in the design at any given time. I tried using set_config_object/get_config_object set_config_object("*", "mem_model_h", mem_model_h, 0); but I guess for that to work my memory model class needs to be derived from the ovm_object class. I am not sure at this point if I will be needing other functions provided by ovm_component class hence I am not sure if that is the solution. I guess I am looking for one of the two things, 1. Passing the handle to this mem_model to all components in the hierarchy. 2. Instantiate the mem model outside of the env and have it provide some helper functions similar to friend functions in C which can then be used by thr other components. Also my env is based in OVM so I am looking for only OVM based solutions. Appreciate any response. Thanks.