[SystemC and latency simulation]

Hi all,

I guess this is a basic question but I can't find the answer. I have a SystemC module that performs several complex arithmetic operation ( several multiplication ). When I simulate it I can see it performs all those operations in on clock cycle after I provided the input. I'm pretty sure that when I'll feed the HLS tool, the tool will pipeline the operation adding latency. Is there any way to manually add latency in order to match what I guess will be the result of the HLS ? I guess I can simulate the latency changing the SC_METHOD with a SC_THREAD and adding a sort of counter, but I was wondering if there is a more elegant and native way to do it.

Cheers.

[Fixed point and quantization mode]

Hi all,

I'm using the SystemC fixed point type (sc_fixed) in one of the modules in my project. This module has to cope with some complex operation ( mainly multiplications and divisions). As you know, when a sc_fixed variable is instantiated I can choose what type of quantization I want among the several available. I've seen that the SC_RND is the one that gives me the better result compared with the same arithmetic but implemented in pure C++ (floating point). I guess that from an hardware point of view the SC_RND is more complicated to implement and slower than for example a SC_TRN. Does anyone knows how big is the drop in terms of timing closure ? Or does anyone know how each quantization mode is implemented in hardware ? I can figure out how the SC_TRN and SC_TRN_ZERO are implemented, but the others are a mistery. Thanks for any reply.

 

Cheers.

[sc_bitref usage]

Hi all,

 

I've a problem pretty stupid I guess. I have this piece of code that doesn't compile at all. I guess the documentation I'm reading is old and something has changed in the SystemC library because this code comes from the documentation:

sc_logic mybit;
sc_uint<8> myint;
mybit = myint[7];

This is what I get:

fde.cpp: In member function ‘void fde::cir_elab()’:
fde.cpp:42:11: error: ambiguous overload for ‘operator=’ (operand types are ‘sc_dt::sc_logic’ and ‘sc_dt::sc_uint_bitref’)
     mybit = myint[7];
           ^

 

I guess I have to do some typecasting but I'm still not really skilled with C++. I've seen I need to use the sc_bitref class, not clear how. Does someone know how to fix this ?

 

Cheers,

Stefano.

 

[2 Complement with sc_fixed type and HLS]

Hi all,

I'm quite new to all the SystemC world. As far as I got the sc_fixed type should be synthesizable. My problem at the moment is that I have a number, and I need the negative version of that number. The easiest way to do it is to multiply for -1. The problem is the HLS. I actually don't know how this it will be handled by the tool. I would like to avoid to instantiate a multiplier just to do a simple 2 complement operation ( flip the bits and adding 1 to the LSB ).

If I can't trust the HLS tools I guess the safest way would be to do the 2 complement by myself, but even there I have some concern :

sc_fixed <8,3,SC_RND,SC_SAT> foo, foo_neg;
foo_neg = ~foo + 2^(8-3)      ( PSEUDOCODE : I still need to figure out )

I don't really like to add 2^-5, it isn't clean. Even here probably it's easier to convert in int and add 1, but still it's quite messy in my opinion. Does anyone know if the tools are smart enough to handle correctly a multiplication between  sc_fixed type  and -1 and to implement correctly the 2 complement operation? If not how should I need to proceed ?

[How to model a delay line in SystemC]

Hi all,

I'm pretty ignorant in SystemC and I've started to learn it so be kind. What is the point to use a delay assignment in a SC_METHOD ? If you are using an SC_METHOD, I guess you are interested to synthesize the module.The delay assignments are basically ignored by the synthesizer and in some cases they can lead to some problems in a soc level verification.

The only use I can think about in VHDL of the delay is to fix the delta delay problem but I'm not sure if the SystemC is affected to this problem.

 

Cheers,

Stefano