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  1. How to model a delay line in SystemC

    Hi all, I'm pretty ignorant in SystemC and I've started to learn it so be kind. What is the point to use a delay assignment in a SC_METHOD ? If you are using an SC_METHOD, I guess you are interested to synthesize the module.The delay assignments are basically ignored by the synthesizer and in some cases they can lead to some problems in a soc level verification. The only use I can think about in VHDL of the delay is to fix the delta delay problem but I'm not sure if the SystemC is affected to this problem. Cheers, Stefano