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enchanter

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Posts posted by enchanter


  1. When I play around with the factory/basic example from uvm-systemc-1.0-beta1, 

    In the original example code, it prints the instance override information as below:

    UVM_INFO @ 0 s: reporter [RNTST] Running test ...
    UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] 
    #### Print Factory Configuration (*)
    
    Instance Overrides:
    
    Requested Type  Override Path  Override Type
      --------------  -------------  -------------
      gen             top.e.gen1     mygen
    Type Overrides:
    
      Requested Type  Override Type
      --------------  -------------
      packet          mypacket
    
    All types registered with the factory: 22 total
      Type Name
      ---------
      env
      gen
      mygen
      mypacket
      packet
      reg_rw
      top
    (*) Types with no associated type name will be printed as <unknown>

    But when I try to comments out the line in factory/basic/top.h (top::build_phase) as below:

            set_inst_override("e.gen1", "gen", "mygen");
            // set_type_override("packet","mypacket");
    

    I expect print factory configuration should still print the instance override but not the type override. But it doesn't print any override.

    UVM_INFO @ 0 s: reporter [RNTST] Running test ...
    UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] 
    #### Print Factory Configuration (*)
    
    No instance or type overrides are registered with this factory
    
    All types registered with the factory: 22 total
      Type Name
      ---------
      env
      gen
      mygen
      mypacket
      packet
      reg_rw
      top
    (*) Types with no associated type name will be printed as <unknown>

     


  2. I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2

    I got error as below and I have no idea what I have done wrong.

    ~/systemc/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h:87:7: error: inherited virtual base class 'sc_core::sc_interface' has private destructor
    class tlm_master_imp :
          ^

     

    I have attached the full compile log

    comp.log


  3. On 27/02/2018 at 9:45 PM, hle said:

    Although the public review is over, I thought it might still be useful to report the issues I had:

    1. The configure script was not present, so I needed to generate it first.
    2. It did not work with systemc-2.3.2 CMake build, UVM-SystemC wanted libsystemc to be in ${SYSTEMC_HOME}/lib-linux64 while it is in ${SYSTEMC_HOME}/lib64.
     

    For the build issue, I think you can over CMake configure in SystemC to set library path to wherever you want. 

     

     


  4. Any plan to fix this build error on Mac OS?

    libtool: link: ar cru .libs/libmacros.a 
    ar: no archive members specified
    usage:  ar -d [-TLsv] archive file ...
        ar -m [-TLsv] archive file ...
        ar -m [-abiTLsv] position archive file ...
        ar -p [-TLsv] archive [file ...]
        ar -q [-cTLsv] archive file ...
        ar -r [-cuTLsv] archive file ...
        ar -r [-abciuTLsv] position archive file ...
        ar -t [-TLsv] archive [file ...]
        ar -x [-ouTLsv] archive [file ...]
    make[4]: [libmacros.la] Error 1 (ignored)
     


  5. 2 hours ago, AmeyaVS said:

    Hello @enchanter,

    After looking into the sources of the UVM-SystemC draft release available here.

    In the following file under: src/uvmsc/base/uvm_root.cpp, line number 150.

    Internally the UVM-SystemC class calls the sc_start() function without any parameter to actually kick start the SystemC simulation.

    Which executes the simulation till events are generated and queued, in your case with clocks the events would always be generated.

    You could create your own function which reproduces the same behavior in the run_test() method of the uvm_root class, or better would be to extend the uvm_root class to suite your needs.

    Here is the code snippet from the UVM-SytemC sources:

    
    // File: src/uvmsc/base/uvm_root.cpp
    // Line number: 127
    void uvm_root::run_test( const std::string& test_name )
    {
      //disable SystemC messages
      sc_core::sc_report_handler::set_actions("/OSCI/SystemC", sc_core::SC_DO_NOTHING);
    
      // check and register test object
      m_register_test(test_name);
    
      // start objection mechanism fired as spawned process
      sc_process_handle m_init_objections_proc =
        sc_spawn(sc_bind(&uvm_objection::m_init_objections),
          "m_init_objections_proc");
    
      uvm_phase::m_register_phases();
      phases_registered = true;
    
      // call build and connect phase
      uvm_phase::m_prerun_phases();
    
    
      // start simulation (of run-phases) here.
      try
      { /////////////////////////////////
        sc_core::sc_start();   //<<<<<<< Run simulation forever or until events exists.
      } ////////////////////////////////
      catch( const std::exception& e )
      {
        std::cerr << e.what() << std::endl;
        exit(1); // TODO exit program with error code?
      }
    
      // TODO: move post-run phases to here? Currently they are part of the simulation
    
      if (m_finish_on_completion)
        sc_core::sc_stop();
    }

    Hope this helps.

    Thanks and Regards,

    Ameya Vikram Singh

     

     

    Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS. 

    When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why. 

     

     


  6. 13 hours ago, AmeyaVS said:

    Hello @enchanter,

    Can you try using sc_start with some appropriate time-period?

    Update: with sc_clock

    e.g.:

    
    // Run the simulation till 100 seconds.
    sc_start(100, SC_SEC);
    // Stop the simulation.
    sc_stop();

    Disclaimer: Currently I do-not have experience much with UVM-SystemC.

    Regards,

    Ameya Vikram Singh

    For UVM, it should not start the simulation by directly call sc_start() and sc_stop(). 


  7. I played with scoreboard/basic example from uvm-systemc package, it finished simulation automatically:

     

    Quote

    80 ns: my_dut received value 9               
    80 ns: my_dut send value 10                  
    80 ns: tb.agent1.monitor received 9          
    80 ns: tb.scoreboard0.rcv_listener received value 9                                       
    80 ns: tb.scoreboard0 rcv_listener in scoreboard received value 9                         
    80 ns: tb.agent2.monitor received 10         
    80 ns: tb.scoreboard0.rcv_listener received value 10                                      
    80 ns: tb.scoreboard0 rcv_listener in scoreboard received value 10                        
    UVM_INFO ../src/sequence.h(65) @ 90 ns: reporter [sequence<REQ,RSP>] Finishing sequence   

    --- UVM Report Summary ---                   

    ** Report counts by severity                 
    UVM_INFO      :   5                          
    UVM_WARNING   :   0                          
    UVM_ERROR     :   0                          
    UVM_FATAL     :   0                          
    ** Report counts by id                       
    [RNTST]                 1                    
    [agent1]                1                    
    [agent2]                1                    
    [sequence<REQ,RSP>]     2                    
    UVM_INFO @ 90 ns: reporter [FINISH] UVM-SystemC phasing completed; simulation finished    
     

    But when I try to add clock signal to the DUT and sc_main as below:

    dut.h

    #ifndef DUT_H_                                                                            
    #define DUT_H_                                                                            
    
    #include <systemc>                                                                        
    
    class dut : public sc_core::sc_module                                                     
    {                                                                                         
     public:                                                                                  
        sc_core::sc_in<int> in;                                                               
        sc_core::sc_in<bool> clk;                                                             
        sc_core::sc_out<int> out;                                                             
    
        void func()                                                                           
        {                                                                                     
            int val;                                                                          
            val = in.read();                                                                  
            std::cout << sc_core::sc_time_stamp() << ": " << name() << " received value " << val << std::endl;                                                                           
            std::cout << sc_core::sc_time_stamp() << ": " << name() << " send value " << val+1 << std::endl;                                                                             
            out.write(val+1);                                                                 
        }                                                                                     
    
        SC_CTOR(dut) : in("in"), out("out")                                                   
        {                                                                                     
            SC_METHOD(func);                                                                  
            sensitive << clk.pos();                                                           
        }                                                                                     
    
    };                                                                                        
    
    #endif /* DUT_H_ */          

    sc_main.cpp

    #include <systemc>                                                                        
    #include <uvm>                                                                            
    
    #include "testbench.h"                                                                    
    #include "dut.h"                                                                          
    #include "vip_if.h"                                                                       
    
    int sc_main(int, char*[])                                                                 
    {                                                                                         
        // instantiate the DUT                                                                
        sc_core::sc_time CLK_PERIOD(10, sc_core::SC_NS);                                      
    
        sc_core::sc_clock clk("clk", CLK_PERIOD, 0.5);                                        
    
        dut* my_dut = new dut("my_dut");                                                      
        testbench* tb = new testbench("tb");                                                  
    
        //uvm_config_db_options::turn_on_tracing();                                           
    
        vip_if* dut_if_in = new vip_if();                                                     
        vip_if* dut_if_out = new vip_if();                                                    
    
        uvm::uvm_config_db<vip_if*>::set(0, "tb.agent1.*", "vif", dut_if_in);                 
        uvm::uvm_config_db<vip_if*>::set(0, "tb.agent2.*", "vif", dut_if_out);                
    
        my_dut->clk(clk);                                                                     
        my_dut->in(dut_if_in->sig_data);                                                      
        my_dut->out(dut_if_out->sig_data);                                                    
    
        uvm::run_test();                                                                      
    
        return 0;                                                                             
    }               

    The simulation will not stop and I have to kill the process. 

    Quote

    1207770 ns: my_dut send value 10
    1207780 ns: my_dut received value 9
    1207780 ns: my_dut send value 10
    1207790 ns: my_dut received value 9
    1207790 ns: my_dut send value 10
    1207800 ns: my_dut received value 9
    1207800 ns: my_dut send value 10
    1207810 ns: my_dut received value 9
    1207810 ns: my_dut send value 10
    1207820 ns: my_dut received value 9
    1207820 ns: my_dut send value 10
    1207830 ns: my_dut received value 9
    1207830 ns: my_dut send value 10
    1207840 ns: my_dut received value 9
    1207840 ns: my_dut send value 10
    1207850 ns: my_dut received value 9
    1207850 ns: my_dut send value 10
    1207860 ns: my_dut received value 9
    1207860 ns: my_dut send value 10
    1207870 ns: my_dut received value 9
    1207870 ns: my_dut send value 10
    1207880 ns: my_dut received value 9
    1207880 ns: my_dut send value 10
    1207890 ns: my_dut received value 9
    1207890 ns: my_dut send value 10
    1207900 ns: my_dut received value 9
    1207900 ns: my_dut send value 10
    1207910 ns: my_dut received value 9
    1207910 ns: my_dut send value 10
    1207920 
     

     

    scoreboard_basic.tar.gz2


  8. I am learning the TLM example at_4_phase in the SystemC 2.3.1 package.

     

    But I don't know why there are 16 WRITE commands are generated by the traffic_generator?

     

    From my understanding, the m_transaction_queue is enqueue-ed twice. So I think it should only generate 2 commands then the queue should be empty. Why it generate 16 WRITE and 16 READ commands instread?


  9. The idea of the quantum is that a process does *not* give up to the scheduler until it decides enough local time has passed. For instance, imagine the current time (as returned by sc_time_stamp()) is 1000ns.

    My initiator has a local sc_time variable t. I initialise t to e.g. 10 ns.

    An initiator thread executes b_transport(tx, t);

     

    What's the local time for target when it received b_transport call, 1000ns or 1010ns?

     

     

     

    The target which implements b_transport, now updates t by 100ns i.e. t now contains 110ns. In other words, the target is "pretending" it took 100ns to process my request, and my local "pretend" time is 1110ns.

     

    the target executes b_transport(tx, t), in which, t should be 100ns or 110ns?


  10. Read some examples about TLM and find the calls about "b_transport" with delay. But all of them just ignore it in the implementation. 

     

    The sc_time_stamp() from both initiator and target are the same value in the print message. So I am not sure what's the "delay" should be used? 

     

    I should wait for "delay" time to start processing request or process the request as soon as possible with my "processing delay" then wait for "delay" time or something else?

     

    Thanks.

     

     


  11. Hello,

    It is not clear if you are looking for a Makefile to compile your

    own modules or the SystemC library. If it is the SystemC

     library, please use the provided Makefiles and follow the

    instructions in the INSTALL file. In most cases, for one's

    own modules, a Makefile is not necessary - on Linux simple

    command line arguments work fine, and if a large number of

    modules are involved, a short shell script works fine.

     

    I try to find a simple template which can compile both the example code and my own (in the future).

     

    The reason why I want one for the example code is I may try to do some modification on the example code to try things, it is too hard for me to tweak the original Makefile in the package.

     

    About the command line, I think that is not a good idea. There's so many flags you have to remember for just compile a single file. I consider Makefile is more productive. 


  12. Why is it you don't want the elements of array a to be randomized? If it is because you want the array values to be 0, then just add that constraint - foreach(a) a == 0;

     

    Most time, I expect random value to test DUT. But sometimes I hope to get some simple patterns to test my verification environment, for example I expect the size is random but the value are constant or in/decreasing etc.

     

    If I use foreach, could I turn it off when I expect random value?


  13. I have a dynamic array in sequence item as below:

     

    rand int array_size;

    rand int a [];

     

    constraint c_order {solve array_size before a;};

    constraint c_size { a.size() == array_size;};

     

     

    In some tests, I hope to only create the array according to the randomized value of array_size but not do randomize on the value of it. Is there any way I can do that?

     

     


  14. I try to define a sc_vector like this in SC_MODULE

     

    sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE); 

     

    Then I got this error:


    expected identifier before string constant

       sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE);

                                                                                          ^    

     

     

    I am not sure what is missing from there. 


     


  15. I am using QuestaSim 10.3a_1 and try to record a dynamic array in the sequence item. But it doesn't show in the waveform window. When I try to fix the array size and use uvm_field_sarray_int to record it, it works well and data show as expected in the waveform windows.


    My code:




    # sequence item
    parameter int P_BIT_DEPTH = 10;
    rand int unsigned data_len;
    rand bit unsigned [P_BIT_DEPTH-1:0] data [];
    ...
    `uvm_field_array_int(data, UVM_ALL_ON+UVM_UNSIGNED)
    `uvm_field_int (data_len, UVM_ALL_ON+UVM_UNSIGNED)
    ...
    constraint c_data_size { data.size() == data_len; };
    constraint c_data_size_order { solve data_len before data; };

    # Sequence body task
    start_item(req);
    if (! req.randomize() with { data_len == 2; })
    `uvm_error(tID, "Can't randomize ingress packet")
    finish_item(req);
     

    req.sprintf() always prints the right information, no matter data is dynamic or static array.


    post-1859-0-04386200-1401142558_thumb.png


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