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enchanter

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Everything posted by enchanter

  1. I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2 I got error as below and I have no idea what I have done wrong. ~/systemc/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h:87:7: error: inherited virtual base class 'sc_core::sc_interface' has private destructor class tlm_master_imp : ^ I have attached the full compile log comp.log
  2. When I play around with the factory/basic example from uvm-systemc-1.0-beta1, In the original example code, it prints the instance override information as below: UVM_INFO @ 0 s: reporter [RNTST] Running test ... UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] #### Print Factory Configuration (*) Instance Overrides: Requested Type Override Path Override Type -------------- ------------- ------------- gen top.e.gen1 mygen Type Overrides: Requested Type Override Type -------------- ------------- packet mypacket All types registered with the factory: 22 total Type Name --------- env gen mygen mypacket packet reg_rw top (*) Types with no associated type name will be printed as <unknown> But when I try to comments out the line in factory/basic/top.h (top::build_phase) as below: set_inst_override("e.gen1", "gen", "mygen"); // set_type_override("packet","mypacket"); I expect print factory configuration should still print the instance override but not the type override. But it doesn't print any override. UVM_INFO @ 0 s: reporter [RNTST] Running test ... UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] #### Print Factory Configuration (*) No instance or type overrides are registered with this factory All types registered with the factory: 22 total Type Name --------- env gen mygen mypacket packet reg_rw top (*) Types with no associated type name will be printed as <unknown>
  3. For the build issue, I think you can over CMake configure in SystemC to set library path to wherever you want.
  4. enchanter

    UVM-SystemC 1.0-beta1 Released

    Any plan to fix this build error on Mac OS? libtool: link: ar cru .libs/libmacros.a ar: no archive members specified usage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...] make[4]: [libmacros.la] Error 1 (ignored)
  5. enchanter

    UVM-SystemC 1.0-beta1 Released

    In installed uvm-systemc.pc file, it sets Libs to "-luvm". Should it be "-luvm-systemc"?
  6. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  7. That is a great news. Will this time add some examples about how to driving clock/reset signal as I ask in this post?
  8. Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS. When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why.
  9. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
  10. For UVM, it should not start the simulation by directly call sc_start() and sc_stop().
  11. I played with scoreboard/basic example from uvm-systemc package, it finished simulation automatically: But when I try to add clock signal to the DUT and sc_main as below: dut.h #ifndef DUT_H_ #define DUT_H_ #include <systemc> class dut : public sc_core::sc_module { public: sc_core::sc_in<int> in; sc_core::sc_in<bool> clk; sc_core::sc_out<int> out; void func() { int val; val = in.read(); std::cout << sc_core::sc_time_stamp() << ": " << name() << " received value " << val << std::endl; std::cout << sc_core::sc_time_stamp() << ": " << name() << " send value " << val+1 << std::endl; out.write(val+1); } SC_CTOR(dut) : in("in"), out("out") { SC_METHOD(func); sensitive << clk.pos(); } }; #endif /* DUT_H_ */ sc_main.cpp #include <systemc> #include <uvm> #include "testbench.h" #include "dut.h" #include "vip_if.h" int sc_main(int, char*[]) { // instantiate the DUT sc_core::sc_time CLK_PERIOD(10, sc_core::SC_NS); sc_core::sc_clock clk("clk", CLK_PERIOD, 0.5); dut* my_dut = new dut("my_dut"); testbench* tb = new testbench("tb"); //uvm_config_db_options::turn_on_tracing(); vip_if* dut_if_in = new vip_if(); vip_if* dut_if_out = new vip_if(); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent1.*", "vif", dut_if_in); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent2.*", "vif", dut_if_out); my_dut->clk(clk); my_dut->in(dut_if_in->sig_data); my_dut->out(dut_if_out->sig_data); uvm::run_test(); return 0; } The simulation will not stop and I have to kill the process. scoreboard_basic.tar.gz2
  12. The SystemC 2.3.2 has been release, does anyone work on make it support the new version? And also supports modern C++ (11, 14, 17)?
  13. I am learning the TLM example at_4_phase in the SystemC 2.3.1 package. But I don't know why there are 16 WRITE commands are generated by the traffic_generator? From my understanding, the m_transaction_queue is enqueue-ed twice. So I think it should only generate 2 commands then the queue should be empty. Why it generate 16 WRITE and 16 READ commands instread?
  14. enchanter

    b-transport interface

    What's the local time for target when it received b_transport call, 1000ns or 1010ns? the target executes b_transport(tx, t), in which, t should be 100ns or 110ns?
  15. Read some examples about TLM and find the calls about "b_transport" with delay. But all of them just ignore it in the implementation. The sc_time_stamp() from both initiator and target are the same value in the print message. So I am not sure what's the "delay" should be used? I should wait for "delay" time to start processing request or process the request as soon as possible with my "processing delay" then wait for "delay" time or something else? Thanks.
  16. I start to learn SystemC and SCV. But I don't have much experience on complex Makefile as the one provided in the install package by SCV. It is too hard for me to understand who the files are really compiled. I am not sure if any one can provide simple Makefile template (Only Linux platform is OK). Thanks.
  17. I try to find a simple template which can compile both the example code and my own (in the future). The reason why I want one for the example code is I may try to do some modification on the example code to try things, it is too hard for me to tweak the original Makefile in the package. About the command line, I think that is not a good idea. There's so many flags you have to remember for just compile a single file. I consider Makefile is more productive.
  18. I have a dynamic array in sequence item as below: rand int array_size; rand int a []; constraint c_order {solve array_size before a;}; constraint c_size { a.size() == array_size;}; In some tests, I hope to only create the array according to the randomized value of array_size but not do randomize on the value of it. Is there any way I can do that?
  19. Most time, I expect random value to test DUT. But sometimes I hope to get some simple patterns to test my verification environment, for example I expect the size is random but the value are constant or in/decreasing etc. If I use foreach, could I turn it off when I expect random value?
  20. I try to define a sc_vector like this in SC_MODULE sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE); Then I got this error: expected identifier before string constant sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE); ^ I am not sure what is missing from there.
  21. I am using QuestaSim 10.3a_1 and try to record a dynamic array in the sequence item. But it doesn't show in the waveform window. When I try to fix the array size and use uvm_field_sarray_int to record it, it works well and data show as expected in the waveform windows. My code: # sequence item parameter int P_BIT_DEPTH = 10; rand int unsigned data_len; rand bit unsigned [P_BIT_DEPTH-1:0] data []; ... `uvm_field_array_int(data, UVM_ALL_ON+UVM_UNSIGNED) `uvm_field_int (data_len, UVM_ALL_ON+UVM_UNSIGNED) ... constraint c_data_size { data.size() == data_len; }; constraint c_data_size_order { solve data_len before data; }; # Sequence body task start_item(req); if (! req.randomize() with { data_len == 2; }) `uvm_error(tID, "Can't randomize ingress packet") finish_item(req); req.sprintf() always prints the right information, no matter data is dynamic or static array.
  22. Hi Philipp: Thanks for your clear explanation.
  23. I have a top level module with template like this: template <int TOP_DEPTH=10> SC_MODULE(my_top){} And I have several sub modules like this: template <int DEPTH=10> SC_MODULE(sub_module_xxx> I try to instantiate sub modules with the modified DEPTH from top level: const int DEPTH_MODULE_A = <math1 on TOP_DEPTH> const int DEPTH_MODULE_B = <math2 on TOP_DEPTH> ... sub_module_a<DEPTH_MODULE_A> *pSubModuleA; sub_module_b<DEPTH_MODULE_B> *pSubModuleB; ... I got compile error about "invalid use of non-static data member". I am not sure what's the right way to do it in C++. (I don't want DEPTH_MODULE_xxx to be static, because my top_module may be used as submodule in other project with different value of TOP_DEPTH. )
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