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mzio

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  1. I have a hierarchical design and I have a problem with the clock signal. Consider top module A where the clock is generated, a module B inside of it with sc_in<bool> clk port bound to sc_clock signal. Inside of module B I instantiate other modules, some of them with sc_in<bool> clk port. When I try to connect the clock port of the modules inside B I get a segmentation fault, that's gdb output: Thread 2 "ctrl_interface" received signal SIGSEGV, Segmentation fault. [Switching to Thread 0x7ffff6789700 (LWP 23216)] 0x000000000042bb93 in sc_core::sc_port_base::insert_parent(int) () During the debug, if I remove the clock port of the modules inside B I don't get any segmentation fault. Every clock port in this hierarchical design is sc_in<bool>, not sc_in_clk. Any suggestions?
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