Bhagwan Jha replied to Somasekhar's topic in UVM SystemVerilog DiscussionsHello Somasekhar, UVM_Sequence has a body method and communication between driver and sequencer, so we must follow some steps as shown below. 1.create_item() / create req. 2.wait_for_grant(). 3.randomize the req. 4.send the req. 5.wait for item done. 6.get response(optional). As per your question, `uvm_do:- This macro takes seq_item or sequence as an argument. On calling `uvm_do() the above-defined 6 steps and start_item and finish_item will be executed. `uvm_create:- This macro creates the item or sequence. `uvm_send:- create() and randomize() are skipped, rest all other steps are executed. start_item():- Tells the sequencer that your sequence is available for arbitration by the sequencer. When it returns, your sequence should then set the variables in your sequence_item to the required values (i.e. by randomization or manual methods) finish_item():- when all the steps are executed in body method then call finish_item() to finish the transactions. Note : start_item() and finish_item() calls do not call pre or post_body(). Thanks, Bhagwan Jha Agnisys Inc.