Amit K Jain started following Where to create regmodel? ...in the test or the env?
Amit K Jain replied to mooredan's topic in UVM SystemVerilog DiscussionsHi Dan, I have created a register layering example and I preferred to create object of class extended from "uvm_reg_block" in test. As you mentioned, this provided me flexibility to pass references around between reg block and reg adapter, reg predictor and reg sequence. While thinking of moving reg block to env class, ease of use or other issues would really depend on your use model. Communication between reg block and adapter, predictor can be done in env class connect phase as well (You can move adapter, predictor handles creation as well in the env class). If you are looking to keep reg block in test base and then use that in extended test class of different tests, I could see use of that in passing reg block to reg sequences. But that could as well be achieved by passing uvm_reg_block class handle to uvm_resource_db and then access that from reg sequence. So I think both the way should be OK (Though I haven't tried having reg block in env class yet, but if there is any specific pitfall then some expert on this forum could help us). I preferred to have in test class, as I like having direct dotted access to refer objects rather than pass using uvm config or resource db. I am not sure if I could help you much using above answer, but please let me know and I can provide you reference with example code snippets if needed. Thanks, Amit