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ralph.goergen

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ralph.goergen last won the day on November 22

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About ralph.goergen

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  1. cannot understand error

    Hi. Seems as if the compiler is confused by too many implicit casts. Could you try explicit read: XMT_datareg=data_bus.read(); Should save one implicit conversion and might help. Actual root cause could be in the _ap_sc stuff (synthesizer internals?). Greetings Ralph
  2. Delta Cycle and concurrency

    Hi. Maybe you should have a look at SystemC AMS. It offers the TDF (timed data flow) model of computation. It follows the data flow concept, i.e. you have a cluster of blocks; the solver defines an order of evaluation of each block; and in every time step, the blocks (or modules) are evaluated in that order. The output of one block is immediately visible at the input of the following block. Greetings Ralph
  3. Hi. This seems to be related to SystemC in general and not to UVM. sc_start() - without argument - starts the simulation until there is no activity anymore. No activity means no more events in the event queue. sc_clock generates new events all the time because the value changes independent from everything else in your design. As a result, the event queue will never be empty and the simulation never stops. (For completemess: the simulation ends as well when the maximum time is reached, i.e. the maximum time value that can be represented by sc_time). Normally, there are two ways to stop simulation, either by calling sc_start with a argument or by calling sc_stop. The first has been mentioned already by AmeyaVS. It runs the simulation for the given time and stops. The second can be done for instance from a testbench thread, e.g. from a sequencer when all sequences are done. Greetings Ralph
  4. Hi. Normally the initiator is considered as owner of the payload, i.e. he should take care of allocating and de-allocating it. The target should decide how to use the data. If the target wants to keep it/store it, the target should make a copy of the data. In that sense, the transaction is completed when b_transport returns because the initiator transfered it to the target and the target had a chance to handle it. A benefit of this is that you do not need dynamic allocation of the buffer buf. Greetings Ralph
  5. SC_CTOR initialization error ???

    Hi. You cannot do an array or a std::vector of SystemC modules. Both would require a default constructor which is not available for sc_modules. Use sc_vector instead. See Section 8.5 in the SystemC LRM (IEEE 1666:2011). Regards Ralph
  6. Hi. The line you posted shows the wrong order of libs. They should be in opposite order of their dependencies, i.e. first systemc-ams the systemc. The same should be done for the object files. Some compilers expect the correct order for them as well. And are you sure that you compiled both libs (systemc and systemc-ams) with the same compiler and settings? Are you sure that there are no remainders of the gcc4.9 experiments in the libs? Regards Ralph
  7. Converting sc_signal<T1> to sc_signal<T2>

    Hi Roman, Why reference? Because handing over variabels as const reference should be default whenever you don't have a good reason to do something else. When a signal contains a complex data type and not only an int, you do not want to copy it with every read. From your example, I am not sure if I got your scenario well. So, returning a const reference is normally not a problem. It is the same as normal sc_signal does. If your problem is that '*host_ptr' changes without temp_val being updated, you need to get grip on its write or update method and implement a write-through to temp_val. And this leads you to implementing a channel. Actually you did implement something like a primitive channel. So, implementing a full primitive channel that allows to be bound to different types could help. But this requires some thoughts and effort. Or you do it the easy, classical way with an hierarchical conversion channel. I would not expect the performance impact of the additional method to be very critical. In some cases, the additional delta cycle can be more problematic, mainly when this affects the clock edge. In both cases, you can benefit from knowing the direction of data transfer and conversion and reduce effort in comparison to using normal signals. Greetings Ralph
  8. TLM 1.0 => TLM 2.0

    Hi. AFAIK, there is nothing like that. In TLM1 communication is based on fifos. In TLM2 it is sockets and transport calls. This is a big difference. TLM2 is conceptually different and not just a slight improvement over TLM1. What you need is a channel that does the conversion from fifo content to payload and transport calls. This is not straightforward and not possible in a generic way. Greetings
  9. Hi. Using -isystem is OK to specify includes. But the path you give it should point to your SystemC installation. Are the SystemC header files in the idrectory you specified? libs/systemc-2.3.1a/include This is alocal path relative to the location where you do the compiler call. Greetings Ralph
  10. systemC

    Dear Yosri, There are so many issues in your code that it is very hard to discuss and fix it in this forum. Please start with learning some basics about SystemC and C++ first. The following tutorial (I mentioned this already earlier) is good as a starting point: https://www.doulos.com/knowhow/systemc/tutorial/ Many people like the following book to learn more: http://www.springer.com/de/book/9780387699578 For more general C++, you can find hundrefs of books and tutorials in the internet. Greetings Ralph
  11. my first program systemC

    Hi. You can find a good starting point for SystemC at: https://www.doulos.com/knowhow/systemc/tutorial/ In general: in the sc_main function, you should first instantiate your modules and bind the ports. Then you should call sc_start. And, you should not call the process methods explicitly. Greetings Ralph
  12. Hi makiso, Please write down all the indexes (values of j) that will be considered in your nested loop (or use cout to print them). The you will see that you do not go through your array. Or consider using sc_vector and the vector based binding facilities to avoid this problem. Greetings Ralph
  13. Read Memory Acess Violation

    Hi. You cannot have C-style arrays of SystemC objects. This includes ports, modules, and *signals*. Use sc_vector instead. BTW: I think it should be possible to drop an sc_vector in an sc_vector to realize two dimensions. Greetings Ralph
  14. What is the scope of dont_initialize()?

    Hi. Ameya is right. See SystemC LRM (ieee1666) Section 5.2.15: [...] it is associated with the most recently created process instance [...] I.e.: ONE process created most recently before calling dont_initialize is not execute. BTW: No process is executed in the constructor. But all processes, that are not marked as dont_initialize, are evaluated once at simulation start. Greetings Ralph
  15. Hi Sumit. what you are doing here is a hierarchical module. foo is a member, i.e. a submodule of bar. They should not have the same name. If you want bar to be derived from foo, then derive bar from foo instead of sc_module. Then, you instantiation will work. If you want foo to be a submodule of bar, let the derivation as is but fix your initializer lists. You need to forward the name argument to the base class constructor in every class derived from sc_module, i.e. in bar as well. Furthermore, the submodule foo should not have the same name as its parent bar. // constructor Bar(sc_core::sc_module_name name) : sc_module(name) // forward name to base class constructor , foo("foo") // name submodule foo 'foo' { ... Or use the SC_CTOR macro that handles this for you. Greetings Ralph
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