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chefo83

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  1. Hello, I am using UVM RAL (UVM 1.2) and have the following problem. When using explicit prediction and the adapter's flag "supports_byte_enable" is set to 1, and when a bus write transaction happens to a register containing a multi-byte field, sometimes the register is not predicted properly. This happens when the byte_en is not set to all 1's. The adapter's bus2reg() method correctly passes the byte_en value to the uvm_reg_bus_op object, however the uvm_reg_field's "do_predict()" method does not make good use of it. So it happens that when byte_en[0] == 1 the entire multi-byte field is updated, regardless of the value of the other byte_en bits. Similarly, when byte_en[0] == 0 the entire multi-byte field is NOT updated, regardless of the other byte_en bits. In my particular case, I am using APB 2.0 (AMBA 4) with PSTRB and the data width is 16 bits. When a write transaction happens on the APB bus with PSTRB[1:0] == 2'b01 to any given "RW" register containing a single 16-bit field, the entire register is updated in the UVM RAL while only the lower byte (LSByte) is actually written in the RTL. Again, if similar transaction happens with PSTRB[1:0] == 2'b10, the entire register is NOT updated in the UVM RAL while the upper byte (MSByte) is actually written in the RTL. I consider it a bug. Could someone from the UVM working group review and file a Mantis ticket if really needed? Thanks, Stefan Yankov
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