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About agumon9

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    Belgrade, Serbia
  1. Thank you very much for the reply! I successfully did it by adding using namespace uvm; and resetting Eclipse because it did not react without resetting.
  2. Thank you very much for the answer! I will try it! Best regards, Aleksandra Panajotu
  3. Hi all! I am having trouble importing UVM-SystemC library in Eclipse. It does not recognize any of the classes from that library. I installed uvm-systemc-1.0-alpha1 library and I am using Systemc-2.3.1 with Eclipse and Cygwin. When I try to write any of the code, for example: #include <uvm> class packet : public uvm_sequence_item{ }; It labels uvm_sequence_item red and says "Symbol 'uvm_sequence_item' could not be resolved". I added uvm-systemc in properties in library and added include paths to compiler settings in Eclipse.
  4. Hi all! I tried to test my environment with one of the examples I found on a website for SystemC (this one). Here is the code of the example: #include "scv.h" const unsigned ram_size = 256; class rw_task_if : virtual public sc_interface { public: typedef sc_uint<8> addr_t; typedef sc_uint<8> data_t; struct write_t { addr_t addr; data_t data; }; virtual data_t read(const addr_t*) = 0; virtual void write(const write_t*) = 0; }; SCV_EXTENSIONS(rw_task_if::write_t) { public: scv_extensions<rw_task_if::addr_t> addr; scv_extensions<rw_task_if::data_t> data; SCV_EXTENSIONS_CTOR(rw_task_if::write_t) { SCV_FIELD(addr); SCV_FIELD(data); } }; class pipelined_bus_ports : public sc_module { public: sc_in< bool > clk; sc_inout< bool > rw; sc_inout< bool > addr_req; sc_inout< bool > addr_ack; sc_inout< sc_uint<8> > bus_addr; sc_inout< bool > data_rdy; sc_inout< sc_uint<8> > bus_data; SC_CTOR(pipelined_bus_ports) : clk("clk"), rw("rw"), addr_req("addr_req"), addr_ack("addr_ack"), bus_addr("bus_addr"), data_rdy("data_rdy"), bus_data("bus_data") {} }; class rw_pipelined_transactor : public rw_task_if, public pipelined_bus_ports { sc_mutex addr_phase; sc_mutex data_phase; scv_tr_stream pipelined_stream; scv_tr_stream addr_stream; scv_tr_stream data_stream; scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen; scv_tr_generator<sc_uint<8>, sc_uint<8> > write_gen; scv_tr_generator<sc_uint<8> > addr_gen; scv_tr_generator<sc_uint<8> > data_gen; public: rw_pipelined_transactor(sc_module_name nm) : pipelined_bus_ports(nm), addr_phase("addr_phase"), data_phase("data_phase"), pipelined_stream("pipelined_stream", "transactor"), addr_stream("addr_stream", "transactor"), data_stream("data_stream", "transactor"), read_gen("read",pipelined_stream,"addr","data"), write_gen("write",pipelined_stream,"addr","data"), addr_gen("addr",addr_stream,"addr"), data_gen("data",data_stream,"data") {} virtual data_t read(const addr_t* p_addr); virtual void write(const write_t * req); }; rw_task_if::data_t rw_pipelined_transactor::read(const rw_task_if::addr_t* addr) { addr_phase.lock(); scv_tr_handle h = read_gen.begin_transaction(*addr); scv_tr_handle h1 = addr_gen.begin_transaction(*addr,"addr_phase",h); wait(clk->posedge_event()); bus_addr = *addr; addr_req = 1; wait(addr_ack->posedge_event()); wait(clk->negedge_event()); addr_req = 0; wait(addr_ack->negedge_event()); addr_gen.end_transaction(h1); addr_phase.unlock(); data_phase.lock(); scv_tr_handle h2 = data_gen.begin_transaction("data_phase",h); wait(data_rdy->posedge_event()); data_t data = bus_data.read(); wait(data_rdy->negedge_event()); data_gen.end_transaction(h2); read_gen.end_transaction(h,data); data_phase.unlock(); return data; } void rw_pipelined_transactor::write(const write_t * req) { scv_tr_handle h = write_gen.begin_transaction(req->addr); // ... write_gen.end_transaction(h,req->data); } class test : public sc_module { public: sc_port< rw_task_if > transactor; SC_CTOR(test) { SC_THREAD(main); } void main(); }; class write_constraint : virtual public scv_constraint_base { public: scv_smart_ptr<rw_task_if::write_t> write; SCV_CONSTRAINT_CTOR(write_constraint) { SCV_CONSTRAINT( write->addr() <= ram_size ); SCV_CONSTRAINT( write->addr() != write->data() ); } }; inline void process(scv_smart_ptr<int> data) {} inline void test::main() { // simple sequential tests for (int i=0; i<3; i++) { rw_task_if::addr_t addr = i; rw_task_if::data_t data = transactor->read(&addr); cout << "at time " << sc_time_stamp() << ": "; cout << "received data : " << data << endl; } scv_smart_ptr<rw_task_if::addr_t> addr; for (int i=0; i<3; i++) { addr->next(); rw_task_if::data_t data = transactor->read( addr->get_instance() ); cout << "data for address " << *addr << " is " << data << endl; } scv_smart_ptr<rw_task_if::write_t> write; for (int i=0; i<3; i++) { write->next(); transactor->write( write->get_instance() ); cout << "send data : " << write->data << endl; } scv_smart_ptr<int> data; scv_bag<int> distribution; distribution.push(1,40); distribution.push(2,60); data->set_mode(distribution); for (int i=0;i<3; i++) { data->next(); process(data); } } class design : public pipelined_bus_ports { list< sc_uint<8> > outstandingAddresses; list< bool > outstandingType; sc_uint<8> memory[ram_size]; public: SC_HAS_PROCESS(design); design(sc_module_name nm) : pipelined_bus_ports(nm) { for (unsigned i=0; i<ram_size; ++i) { memory[i] = i; } SC_THREAD(addr_phase); SC_THREAD(data_phase); } void addr_phase(); void data_phase(); }; inline void design::addr_phase() { while (1) { while (addr_req.read() != 1) { wait(addr_req->value_changed_event()); } sc_uint<8> _addr = bus_addr.read(); bool _rw = rw.read(); int cycle = rand() % 10 + 1; while (cycle-- > 0) { wait(clk->posedge_event()); } addr_ack = 1; wait(clk->posedge_event()); addr_ack = 0; outstandingAddresses.push_back(_addr); outstandingType.push_back(_rw); cout << "at time " << sc_time_stamp() << ": "; cout << "received request for memory address " << _addr << endl; } } inline void design::data_phase() { while (1) { while (outstandingAddresses.empty()) { wait(clk->posedge_event()); } int cycle = rand() % 10 + 1; while (cycle-- > 0) { wait(clk->posedge_event()); } if (outstandingType.front() == 0) { cout << "reading memory address " << outstandingAddresses.front() << " with value " << memory[outstandingAddresses.front()] << endl; bus_data = memory[outstandingAddresses.front()]; data_rdy = 1; wait(clk->posedge_event()); data_rdy = 0; } else { cout << "not implemented yet" << endl; } outstandingAddresses.pop_front(); outstandingType.pop_front(); } } int sc_main (int argc , char *argv[]) { scv_startup(); scv_tr_text_init(); scv_tr_db db("my_db"); scv_tr_db::set_default_db(&db); // create signals sc_clock clk("clk", 20, SC_NS, 0.5, 0, SC_NS, true); sc_signal< bool > rw; sc_signal< bool > addr_req; sc_signal< bool > addr_ack; sc_signal< sc_uint<8> > bus_addr; sc_signal< bool > data_rdy; sc_signal< sc_uint<8> > bus_data; // create modules/channels test t("t"); rw_pipelined_transactor tr("tr"); design duv("duv"); // connect them up t.transactor(tr); tr.clk(clk); tr.rw(rw); tr.addr_req(addr_req); tr.addr_ack(addr_ack); tr.bus_addr(bus_addr); tr.data_rdy(data_rdy); tr.bus_data(bus_data); duv.clk(clk); duv.rw(rw); duv.addr_req(addr_req); duv.addr_ack(addr_ack); duv.bus_addr(bus_addr); duv.data_rdy(data_rdy); duv.bus_data(bus_data); // run the simulation sc_start(1000000, SC_NS); return 0; } It's nothing much. The transactor and the DUV are extended classes of the module and the transactor generates the address and sends it to the DUV and the DUV reads the data from memory with that address. Everything looks fine but when I try to run it i get error: TB Transaction Recording has started, file = my_db Transaction Recording is closing file: my_db Error: (E115) sc_signal<T> cannot have more than one driver: signal `signal_5' (sc_signal) first driver `duv.bus_data' (sc_inout) second driver `tr.bus_data' (sc_inout) In file: ../../../../src/sysc/communication/sc_signal.cpp:73 I can't see where are multiple drivers when only the DUV sends that signal and the transactor only reads the signal. Even if I delete all of the lines that do anything with this signal it still shows the same error.
  5. Thank you so much! I have been struggling with this for a while! It makes sense but I didn't think of it. It works perfectly!
  6. Hi! I am having a problem with not being able to build any code that contains any usage of SCV functions. This is a simple code that I am trying to build and run: #include <scv.h> int sc_main (int argc, char* argv[]) { // Int data type int data = 100; // Get the bitwidth of the data int bitwidth = scv_get_extensions(data).get_bitwidth(); cout << "Width of data is "<< bitwidth << endl; cout << "Value in data is "; // Get the value in data and print to stdio scv_get_extensions(data).print(); return 0; } but it has a ton of errors, mostly repeating themselves. This is a first couple of them: Building target: proba.exe Invoking: Cygwin C++ Linker g++ -L"C:/systemc-2.3.1/lib-cygwin" -o "proba.exe" ./apb_transaction.o -lsystemc -lscv C:/systemc-2.3.1/lib-cygwin/libscv.a(libscv_la-scv_introspection.o): In function `_scv_extension_rw_sc_signed::write(sc_dt::sc_signed const&)': /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090: undefined reference to `sc_dt::sc_signed::operator=(sc_dt::sc_signed const&)' /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090:(.text+0xee54): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `sc_dt::sc_signed::operator=(sc_dt::sc_signed const&)' C:/systemc-2.3.1/lib-cygwin/libscv.a(libscv_la-scv_introspection.o): In function `_scv_extension_rw_sc_signed::assign(long)': /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090: undefined reference to `sc_dt::sc_signed::operator=(long)' /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090:(.text+0xf04e): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `sc_dt::sc_signed::operator=(long)' C:/systemc-2.3.1/lib-cygwin/libscv.a(libscv_la-scv_introspection.o): In function `_scv_extension_rw_sc_signed::assign(unsigned long)': /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090: undefined reference to `sc_dt::sc_signed::operator=(unsigned long)' /cygdrive/c/scv-2.0.0/objdir/src/scv/../../../src/scv/scv_introspection.cpp:1090:(.text+0xf08a): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `sc_dt::sc_signed::operator=(unsigned long)' I am using Eclipse with Cygwin.
  7. I did it! If anyone else needs it: there should be libscv.a and libscv.la in lib-cygwin folder in systemc folder after installation of scv library. So just go to the project you are working on in Eclipse -> Properties -> C/C++ Build -> Settings -> Cygwin C++ Linker and add scv to the libraries list! Thank you, Stephan, for all the help!
  8. I was finally able to call $ make without it getting any errors. There is an error in scv-2.0.0\src\scv\scv_init_seed.cpp: it should include sys\time.h instead of time.h because struct timezone that could not be found is defined in sys\time.h. Now $ make went trough without errors and $ make install and $ make check showed no errors. How can I connect this library to be used in Eclipse?
  9. Firstly, thanks for all the help. I have followed SystemC-2.3.1 INSTALL manual and done everything it said. Then I downloaded scv-2.0.0 and somehow called $ configure and it showed no errors. Then i called $ make and it showed a ton of text and in the end showed errors i copied two posts before. I called $ make install and it also wrote out a ton of text and printed the same two errors. I am a bit stuck here. I need to use SCV in Eclipse but i cannot include <scv.h>. Eclipse doesn't see the scv.h file.
  10. I am getting those errors in Cygwin when I execute $ make and $ make install. I tried to use it in eclipse but it wont include scv.h file. Eclipse says C:/systemc-2.3.1/include/scv.h:44:26: fatal error: scv/scv_util.h: No such file or directory
  11. my reply probably got lost. Anyway, I managed to rename folder containing libsystemc.a from lib-cygwin64 to lib-cygwin and it successfully finished configure. Make and make install have these errors ../../../src/scv/scv_init_seed.cpp: In function 'long long unsigned int _scv_default_global_init_seed(long unsigned int)': ../../../src/scv/scv_init_seed.cpp:76:19: error: aggregate '_scv_default_global_init_seed(long unsigned int)::timezone dummy1' has incomplete type and cannot be defined struct timezone dummy1; ^ ../../../src/scv/scv_init_seed.cpp:77:28: error: 'gettimeofday' was not declared in this scope gettimeofday(&tp, &dummy1); ^ make[2]: *** [Makefile:542: libscv_la-scv_init_seed.lo] Error 1 make[2]: Leaving directory '/cygdrive/c/scv-2.0.0/objdir/src/scv' make[1]: *** [Makefile:440: check-recursive] Error 1 make[1]: Leaving directory '/cygdrive/c/scv-2.0.0/objdir/src' make: *** [Makefile:484: check-recursive] Error 1 Will this work anyway?
  12. Thank you for your help! I managed to do it using Vim editor in Cygwin although I still cannot make it work because now it can't find all libraries for systemC in systemc-2.3.1 folder.
  13. Should I change configure.ac or configure file? I tried changing the configure.ac file and it made no difference. Changing configure file made this errors ../configure: line 14: $'\r': command not found ../configure: line 29: syntax error near unexpected token `newline' './configure: line 29: ` ;; even after changing everything back. Only copying old file instead of the changed one would make the error go away.
  14. Hi all! I have a problem adding SCV library. I am new to SystemC! I am using 64bit Windows 7 and I have installed Cygwin x86_64. SystemC works with Eclipse but I am unable to add SCV library. When I try to execute $ ../configure --with-systemc=/cygwin/c/systemc-2.3.1 it writes out numerous lines and then I get errors checking for supported C++ compiler... configure: WARNING: gcc 5.4 is not a supported version (i.e. (3.2|3.4|4.1|4.2|4.3|4.4|4.5|4.6|4.7|4.8)). Beware. checking for supported operating system... configure: error: cygwin is not supported Is there any way to get around this problem?