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sheetal

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  1. Have you tried using the tab file, if you are using VCS. Add rw capability to the memories and the registers you are trying to write using backdoor access, in the tab file as shown below: acc=rw:<MEMORY_NAME> acc=rw:<hierarchical_path_to_reg_block> Pass this tab file on the vcs command line alongwith the switch: +applylearn+<tab_file>
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