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  1. I have two classes, one is block_seq which extends from uvm_sequence and other is block_cfg_mngr which extends from uvm_component. How do I exchange information between these two. I need to generate random values in block_cfg_mngr which depends on the values I generate in the bock_sequence body method. I need a communication mechanism to pass the information from uvm_sequence to uvm_component or vice versa. How can I do that ?
  2. Turn off `uvm_info messages

    Messages with verbosity UVM_NONE are printed by default no matter what value you give to UVM_VERBOSITY. I don't want even that to get printed on the log.
  3. Is there any way to turn off `uvm_info messages being displayed on the log while retaining `uvm_error and `uvm_fatal messages
  4. I have a variable logic [31:0] id which is not declared as rand or randc. I need different id's each time into an array logic [31:0] id_array [16]. logic [31:0] id; logic [31:0] id_array [16]; foreach(id_array) begin std::randomize(id); id_array = id; end In the above code, there is a possibility of getting duplicate ids in the array. How do I change the code to get unique ids in the array ?