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susharmas

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  1. Hello Mohit, May be below mentioned is useful for you: e.notify(SC_TIME_ZERO) is called when all the runnable process is emptied. It is called delayed notification. In other words, process waiting for delayed notification are set to runnable only after all the runnable process are done. wait(SC_TIME_ZERO): A process waiting for zero time will resume its execution after all the runnable process have yielded. Then that process will be next in queue for runnable. notify(void): It may cause one or more process in the waiting set to be moves into the runnable set. wait(void): This lets the thread to use the static sensitivity, and control goes to the next clock cycle. Regards Sunil Sharma
  2. systemc model of d-flip-flop

    Hello Sir, Can you please help me to find out the error in this small code. I am newbie to the SystemC and not able to debug it. I am designing the D flip flop in SystemC. Here below is the code and error: ////////////////////////////////////////////////////////////////////// //dff.cpp ///////////////////////////////////////////////////////////////////// #include "systemc.h" SC_MODULE(dff){ sc_in<bool> din; sc_in<bool> clk; sc_out<bool> out; void func(); SC_CTOR(dff){ SC_THREAD(func); sensitive_pos<<clk; } }; void dff::func() { out.write(din.read()); } //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// AND BELOW IS THE TB FILE: dff_main.cpp /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #include "systemc.h" #include "dff.cpp" int sc_main(int argc, char* argv[]){ sc_signal<bool> din; sc_signal<bool> out; sc_clock clk("clk", 10, 0.5, 0, true); dff inst("inst"); inst.din(din); inst.clk(clk); inst.out(out); sc_start(100, SC_NS); sc_trace_file *tf = sc_create_vcd_trace_file("inst"); sc_trace(tf, din, "din"); sc_trace(tf, clk, "clk"); sc_trace(tf, out, "out"); din.write(0); wait(5, SC_NS); din.write(1); wait(10, SC_NS); din.write(0); wait(15, SC_NS); din.write(1); wait(10, SC_NS); din.write(0); wait(20, SC_NS); din.write(1); wait(10, SC_NS); din.write(0); wait(8, SC_NS); sc_stop(); return (0); } /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// And the error is: ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// \dff.dir/objects.a(dff.cpp.obj):dff.cpp:(.text+0x0): multiple definition of `dff::func()' CMakeFiles\dff.dir/objects.a(dff_main.cpp.obj):dff_main.cpp:(.text+0x0): first defined here collect2.exe: error: ld returned 1 exit status Please help me how to remove this error. Regards Sunil S.
  3. Hello Gerth, It is ModelSim-10.2b simulator. And i am in need of single script that simulate both SystemC and UVM-testbench. Actually i am not able to address both environment via a single script. Please Guide. Regards Sunil S.
  4. Hello Sir, Thanks for reply. 1. It is SystemC reference model. 2. This SystemC reference model need to be verified in UVM-SV testbench. 3. Now my doubt is how to connect this SystemC reference model with the UVM-SV testbench. Both are ready at my end. Here SystemC reference model act as RTL and UVM-SV testbench act as testbench environment for this reference model. 4. Testcases are written in UVM-SV testbench. Pleasse guide me in this regard. Since i am new to SystemC and integration. Regards Sunil S.
  5. Hello Sir, Can you please guide me how to connect the SystemC RTL model and UVM testbench. Please help in this regard. Regards Sunil S.
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