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upputuri92

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  1. upputuri92

    Parameterised module instantiation

    can u explain in detail....i know it can done in VHDL by for loop for port connections and generate statement for instantiation...but i dont know in systemC
  2. upputuri92

    Parameterised module instantiation

    Hey ralph, I have connect 16 D-Flipflops(submodule) in the form just like 4*4 matrix with Q connecting to the input of next D flipflop in x direction and Q_bar to input of D_flipflop in Y direction....could you suggest a way unlike instantiating a 16 modules like DFF11,DFF2...........DFF16. please suggest a way for multiple instantiations (paramaterized instantiation ) and can we do portmapping using for loop in systemC??
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