wilson_on posted a topic in UVM SystemVerilog DiscussionsIs clock(signal from rtl or from testbench) allow to be used in C program to trigger event or delay?
wilson_on posted a topic in UVM SystemVerilog DiscussionsHi, I am new to Python and I have been asked to build a UVM testbench which can call Python functions. Is there any way that I can do which is similar to DPI-C for C functions in verilog testbench? If you can provide a detail example, that would be great. Thanks.