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  1. basarts

    SystemVerilog "program" scope

    From a hardware verification point of view, a simple solution would be to let the SC TB sample on the falling clock edge i.s.o. the same rising edge.
  2. Hi Karthick, Thanks for your reply. I did mean sc_out<double> out_port and sc_in<double> in_port, because I was deliberately using a double channel. The sizeof() operator returns 8 both for double and unsigned long long on my system. In the meantime, I found that it is not related to SystemC anyway: double d = 3.1415926535897931; unsigned long long *ullp = (unsigned long long *) &d; unsigned long long ull = *ullp; // ull = 4614256656552045848 double d2 = (double) ull; // d2 = 4614256656552045568.0000000000000000 !! unsigned long long ull2 = (unsigned long long) d2; // ull2 = 4614256656552045568 double * dp = (double *) &ull2; // *dp = 3.1415926535896688 Hence, the casting of an unsigned long long to a double seems to cause the problem. -- greetz, Bas
  3. I tried to write and read an unsigned long long value over a double channel, using a double value as starting point. Code snippet: double d = 3.1415926535897931; unsigned long long * ullp = (unsigned long long *) &d; out_port.write(*ullp); // sc_out<double> out_port; connected via sc_signal<double> to in_port unsigned long long ull = in_port.read(); // sc_in<double> in_port; connected via sc_signal<double> to out_port double * dp = (double *) &ull; When I print the values of d, *ullp, ull and *dp, I notice the following: d: 3.1415926535897931; *ullp: 4614256656552045848; ull: 4614256656552045568; *dp: 3.1415926535896688; However, plain casting without SystemC (double d -> ull* ullp = (ull*) &d -> ull u = *ullp -> double* dp = (double*) &u -> double d2 = *dp) returns d2 with exactly the same value as d. Any idea what is happening and why the channel of type double seems to loose a bit of its precision when using it in this way? -- greetz, Bas