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A.Elgogary

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A.Elgogary last won the day on January 18 2017

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  1. A.Elgogary

    Mixing Systemc with Systemc AMS

    like this no match for call to ‘(sca_tdf::sca_de::sca_in<double>) (sca_tdf::sca_signal<double>&)’
  2. I have been tring to connect Systemc Modul with SC_METHOD to other parts which is TDF modules, but keep receiving different errors in ports and signals connection , Can some clarify how to do it? Controller have inputs from TDF and sends outputs to it (Systemc) to (Systemc-AMs) TDF
  3. i partially understand you but why it is yielding different results than Matlab? my be because the timestep larger than half of the time constant of the equations but is there is a way to edit it ? without changing the controller timestep which is 10ms ?
  4. Here is an Example which give the same warning : #include "systemc.h" #include "systemc-ams.h" SCA_TDF_MODULE( ModuleIn ) { sca_tdf::sca_in<double> q; sca_tdf::sca_out<double> q2ms; void initialize() { } void set_attributes() { set_timestep(2, SC_MS); } void processing() { q2ms = 0; cout << q << endl; } SCA_CTOR( ModuleIn ) { } }; SCA_TDF_MODULE( ModuleOut ) { sca_tdf::sca_out<double, sca_tdf::SCA_DT_CUT> q; sca_tdf::sca_in<double> q2ms; void initialize() { //q.set_rate(5); } void set_attributes() { q2ms.set_rate(5); set_timestep(10, SC_MS); } void processing() { q = 1; } SCA_CTOR( ModuleOut ) { } }; SC_MODULE( MainModule ) { ModuleOut * ModuleOut0; ModuleIn * ModuleIn0; sca_tdf::sca_signal<double> q, q2ms; SC_CTOR( MainModule ) { ModuleOut0 = new ModuleOut("ModuleOut0"); ModuleOut0->q(q); ModuleOut0->q2ms(q2ms); ModuleIn0 = new ModuleIn("ModuleIn0"); ModuleIn0->q(q); ModuleIn0->q2ms(q2ms); } ~MainModule() { } }; MainModule * MainModule0 = NULL; int sc_main(int argc, char* argv[]) { MainModule0 = new MainModule("MainModule0"); sc_start(100, SC_MS); return 0; } Output: SystemC 2.3.1-Accellera --- Feb 12 2016 19:29:34 Copyright (c) 1996-2014 by all Contributors, ALL RIGHTS RESERVED SystemC AMS extensions 2.1.0-COSEDA Release date: 20160404 Copyright (c) 2010-2014 by Fraunhofer-Gesellschaft IIS/EAS Copyright (c) 2015-2016 by COSEDA Technologies GmbH Licensed under the Apache License, Version 2.0 Info: SystemC-AMS: 2 SystemC-AMS modules instantiated 1 SystemC-AMS views created 3 SystemC-AMS synchronization objects/solvers instantiated Info: SystemC-AMS: 1 dataflow clusters instantiated cluster 0: 3 dataflow modules/solver, contains e.g. module: MainModule0.ModuleOut0 11 elements in schedule list, 10 ms cluster period, ratio to lowest: 5 e.g. module: MainModule0.ModuleIn0 ratio to highest: 1 sample time e.g. module: MainModule0.ModuleOut0 0 connections to SystemC de, 0 connections from SystemC de Warning: SystemC-AMS: Write not called for decoupling outport: MainModule0.ModuleOut0.sca_tdf_out_dt_cut_0 In file: /usr/local/systemc-ams-2.1/include/scams/predefined_moc/tdf/sca_tdf_out_dt_cut.h:507 In process: MainModule0.sca_implementation_0.cluster_process_0 @ 0 s 0 0 0 0 0 Warning: SystemC-AMS: Write not called for decoupling outport: MainModule0.ModuleOut0.sca_tdf_out_dt_cut_0 In file: /usr/local/systemc-ams-2.1/include/scams/predefined_moc/tdf/sca_tdf_out_dt_cut.h:507 In process: MainModule0.sca_implementation_0.cluster_process_0 @ 10 ms
  5. yes it is there and keep repeating SystemC 2.3.1-Accellera --- Feb 12 2016 19:29:34 Copyright © 1996-2014 by all Contributors, ALL RIGHTS RESERVED SystemC AMS extensions 2.1.0-COSEDA Release date: 20160404 Copyright © 2010-2014 by Fraunhofer-Gesellschaft IIS/EAS Copyright © 2015-2016 by COSEDA Technologies GmbH Licensed under the Apache License, Version 2.0
  6. i keep receiving the error (just on time) for TDF Output port with 10ms time step and 5 rate and sca_tdf_out_dt_cut, connected to 2ms TDF model?? Warning: SystemC-AMS: Write not called for decoupling outport: Crane0.Controller0.VC In file: /usr/local/systemc-ams-2.0/include/scams/predefined_moc/tdf/sca_tdf_out_dt_cut.h:390 In process: Crane0.sca_implementation_0.cluster_process_0 @ 0 s
  7. I was using systemc ams 2.3.1 with systemc ams 2.0 beta, i was using State Space model TDF with my controller but i noticed that the result is a function of sampling time , i mean to let SS yield a correct output, sampling time should be 1s, otherwise the output is divided by the sampling time for example if sampling time is 10ms than the result will be divided by 1000 and so on. i created a small example to show what i got, and i need to understand is this behavior correct ? and why ? or it is a bug ? if you changed set_timestep(1, SC_MS); and simmulation time to 2 ms you will see the difference, also i compare to matlab state space model and the one with one sec is the correct. Output with 1s Sampling time Y SS Systemc 0 0 Y Matrix 170 230 Y SS Systemc 170 230 Y Matrix 170 230 Result with 1ms Y SS Systemc 0 0 Y Matrix 170 230 Y SS Systemc 0.17 0.23 Y Matrix 170 230 /* * State-Space.cpp * * Created on: Mar 14, 2016 * Author: elgogary */ #include "systemc.h" #include "systemc-ams.h" #include <Eigen/Dense> using Eigen::MatrixXd; SCA_TDF_MODULE( StateSpace ) { sca_tdf::sca_out< double> q; void initialize() { a(0, 0) = 0; a(0, 1) = 0; a(1, 0) = 0; a(1, 1) = 0; b(0, 0) = 5; b(0, 1) = 6; b(1, 0) = 7; b(1, 1) = 8; c(0, 0) = 1; c(0, 1) = 0; c(1, 0) = 0; c(1, 1) = 1; d(0, 0) = 0; d(0, 1) = 0; d(0, 0) = 0; d(0, 1) = 0; s(0) = 0; s(1) = 0; } void set_attributes() { set_timestep(1, SC_SEC); } void processing() { sca_util::sca_vector<double> x; x(0) = 10; x(1) = 20; //sca_core::sca_time timestep; sca_util::sca_vector<double> y = q_ss(a, b, c, d, s, x ); cout << "Y SS Systemc" << y <<endl; MatrixXd B(2,2); MatrixXd inp(2,1); inp(0,0) = 10; inp(1,0) = 20; B(0, 0) = 5; B(0, 1) = 6; B(1, 0) = 7; B(1, 1) = 8; cout << "Y Matrix" <<endl<< B*inp<<endl; } SCA_CTOR( StateSpace ) : q("q"), a(2,2), b(2,2), c(2,2), d(2,2) { } private: sca_tdf::sca_ss q_ss; // state-space equation sca_util::sca_matrix<double> a, b, c, d; // state-space matrices sca_util::sca_vector<double> s; // state vector }; #include "State-Space.cpp" SC_MODULE( Crane ) { StateSpace * StateSpace0; sca_tdf::sca_signal<double> q; SC_CTOR( Crane ) { StateSpace0 = new StateSpace("StateSpace0"); StateSpace0->q(q); } ~Crane() { delete StateSpace0; } }; Crane * Crane0 = NULL; int sc_main(int argc, char* argv[]) { Crane0 = new Crane("Crane0"); sc_start(2, SC_SEC); return (0); }
  8. A.Elgogary

    problem with tb of fir filter

    i finally managed to compiled it online , i am sure now it is the compiler, will try to install on linux thanks for your help.
  9. A.Elgogary

    problem with tb of fir filter

    I tried many examples and they worked . Can you compiled the files and tell me if they worked or not ?
  10. A.Elgogary

    problem with tb of fir filter

    yes here is the error i got only with clock but some times with sc_signal < bool > only , also i read online and found there is a bug with eclipse generally with c++ The type 'sc_core::sc_clock' must implement the inherited pure virtual method 'sc_core::sc_signal_write_if::write' - Line breakpoint: main.cc [line: 23] also other programs run normally and generate waveforms but only this one stucks after simulation start in main func and the call of constructor in systb above without calling tb as i think.
  11. A.Elgogary

    problem with tb of fir filter

    I added c++11 flag but nothing happened too, also i compilled other projects and it works, is there any way to debug it ?
  12. A.Elgogary

    problem with tb of fir filter

    i was tring to do an online training by fortedesign on youtube and tried to use the same code but after running got nothing, i think the testbench doesn't run at all ? also i got error from eclispe with any sc_signal < bool > ? fir.h #include <iostream> #include "systemc.h" SC_MODULE( fir ){ sc_in < bool > clk; sc_in < bool> rst; sc_in< sc_int<16> > inp; sc_in < bool > inp_vld; sc_out < bool > inp_rdy; sc_out< sc_int<16> > outp; sc_out< bool> outp_vld; sc_in < bool> outp_rdy; void fir_main(); SC_CTOR( fir ){ SC_CTHREAD( fir_main, clk.pos()); reset_signal_is( rst, true); }; }; fir.cc #include "fir.h" const sc_uint< 16 > coef[5] = {18,77,107,77,18}; void fir::fir_main(){ cout << "fir_main oper" << endl; sc_uint< 16 > taps[5]; //rest is wrote here till first wait for (int i = 4; i > 0; i--) { taps[i] = 0; } //intailaize handscack inp_rdy.write(0); outp_vld.write(0); outp.write( 0 ); wait(); while(true){ sc_int < 16 > in_val; sc_int < 16 > out_val; inp_rdy.write(1); do{ wait(); }while(!inp_vld.read()); in_val = inp.read(); inp_rdy.write(0); //read input into shift register for (int i = 4; i > 0; i--) { taps[i] = taps[i-1]; } taps[0] = in_val; // perfom multiplay and accumulate for (int i = 0; i < 5; i++) { out_val += coef[i]*taps[i]; } outp_vld.write(1); outp.write(out_val); do{wait(); }while(!outp_rdy.read()); outp_vld.write(0); wait(); }//while } tb.h #include "systemc.h" #include <iostream> SC_MODULE (tb){ sc_in < bool > clk; sc_out < bool > rst; sc_out< sc_int<16> > inp; sc_out < bool > inp_vld; sc_in < bool > inp_rdy; sc_in< sc_int<16> > outp; sc_in< bool > outp_vld; sc_out < bool > outp_rdy; sc_time starttime[64],endtime[64], clockperiod; void source(); void sink(); FILE *outfp = NULL; SC_CTOR(tb){ SC_CTHREAD ( source, clk.pos()); SC_CTHREAD ( sink, clk.pos()); } }; tb.cc #include "tb.h" void tb::source() { cout << "source" << endl; sc_int < 16 > tmp; //rest inp.write( 0 ); inp_vld.write(0); rst.write( 1 ); wait(); rst.write( 0 ); wait(); for(int i = 0; i < 64; i++) { if (i > 23 && i < 29) tmp = 256; else tmp = 0; inp_vld.write(1); inp.write (tmp); starttime[i] = sc_time_stamp(); do{ wait(); }while(!inp_rdy.read()); inp_vld.write(0); } //hanging prevent wait(10000); printf("sim hang stopped by TB \n"); sc_stop(); } void tb::sink() { cout << "sink" << endl; sc_int <16> datain; //clk peroid sc_clock *clkp = DCAST<sc_clock*>(clk.get_interface()); clockperiod = clkp->period(); //int port outp_rdy.write(0); double totalcycles = 0; //open sim file char output_file[256]; sprintf(output_file, "./output.dat"); outfp = fopen(output_file, "w"); if(outfp == NULL ){ printf("couldn't open output.dat \n"); exit(0); } for(int i=0; i < 64; i++) { outp_rdy.write(1); do{wait(); }while(!outp_vld.read()); datain = outp.read(); endtime[i] = sc_time_stamp(); totalcycles += (endtime[i] - starttime[i]) / clockperiod; outp_rdy.write(0); fprintf(outfp, "%d\n", (int)datain); cout << i << " :\t" << datain.to_double() << endl; } //latancy double throughput = (starttime[63] - starttime[0]) / clockperiod; printf("average latancy is %g cycles.\n", (double)(totalcycles/64)); printf("average throughut is %g cycles/input.\n", (double)(throughput/63)); //end sim sc_stop(); fclose(outfp); cout << "sim stop" << endl; } main.cc #include "systemc.h" #include "fir.h" #include "tb.h" //module connecting fir to tb and run sim SC_MODULE( systb ){ tb * tb0; fir * fir0; sc_signal < sc_int < 16 > > inp_sig; sc_signal < bool > inp_sig_vld; sc_signal < bool > inp_sig_rdy; sc_signal < bool > rst_sig; sc_signal < sc_int < 16 > > outp_sig; sc_signal < bool > outp_sig_vld; sc_signal < bool > outp_sig_rdy; sc_clock clk_sig; SC_CTOR( systb ) : clk_sig ("clk_sig", 10, SC_NS) { cout << "constructor" << endl; tb0 = new tb("tb0"); tb0->clk( clk_sig ); tb0->rst( rst_sig ); tb0->inp( inp_sig ); tb0->inp_vld( inp_sig_vld ); tb0->inp_rdy( inp_sig_rdy ); tb0->outp( outp_sig ); tb0->outp_vld( outp_sig_vld ); tb0->outp_rdy( outp_sig_rdy ); fir0 = new fir("fir0"); fir0->clk( clk_sig ); fir0->rst( rst_sig ); fir0->inp( inp_sig ); fir0->inp_vld( inp_sig_vld ); fir0->inp_rdy( inp_sig_rdy ); fir0->outp( outp_sig ); fir0->outp_vld( outp_sig_vld ); fir0->outp_rdy( outp_sig_rdy ); } ~systb(){ delete tb0; delete fir0; cout << "delete" << endl; } }; systb *top = NULL; int sc_main(int, char* []) { top = new systb("top"); cout << "sim start" << endl; sc_trace_file *fp; fp=sc_create_vcd_trace_file("wave"); fp->set_time_unit(100, SC_PS); sc_trace(fp,top->clk_sig , "clk_sig"); sc_trace(fp,top->rst_sig , "rst_sig"); sc_start(200, SC_NS); sc_close_vcd_trace_file(fp); return 0; } also if there is some reference or training to increase my knowledge with systemc would be more than happy .
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