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  1. Hi, I have a single reg_model file generated from ralgen, Now there are some registers that can be written only using 64b write and some that can be written only using 32b write. What is the best way to implement this using the RAL. Currently based on the offsets that need to be programmed using the 64b. I have tweaked by reg2bus to do a 64b instead of default 32. i heard about tlm extensions that can be used in this regard. Can some one throw some light on the best ways. My way of implementation meets the purpose but looks hacky.
  2. I have a situation where in the IP provided provided IPXACT for the same register with different behavior. Eg: REG B which decides behaviour of REG A bit FIELD D I) REG A bit [4:0] FIELD B II) REG A bit [10:0] FIELD C The reg A behaves like I) when REG B is programmed as 0 and ii) when REG B is programmed to 1. Can you please share thoughts on best ways of implementing this. ?
  3. Hi, i am looking for a solution to implement a RAL which supports both shadow coy and active copy as used by RTL. Basically when a write happens to a particular register, the shadow copy gets updated and based on another register write (update) the shadow copy becomes the active copy. In RTL, the registers are stored in two different signals and is assigned based on the extra signals which gets asserted based on the update. please share some thoughts on implementing same.