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viru_agnisys

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  1. viru_agnisys

    Cadence IPXact -> UVM_REG Register Map generator

    Agnisys product IDesignSpec helps to create the RTL, UVM reg model, right the specification. The specification can be in word, Excel, IP-XACT, SystemRDL etc. Please visit link for more details http://agnisys.com/
  2. viru_agnisys

    OVM RGM Porting to UVM

    IDesignSpec™ - Create Executable Design Code From The Specification – UVM Register GeneratorIDesignSpec™ is an award winning semiconductor design and verification product that allows an IP, chip or system designers to create the register map specification for their digital system once and automatically generate all of the required outputs from it. A wide range of outputs are available such as UVM, OVM, RALF, SystemRDL, IP-XACT and user defined outputs created using Tcl or XSLT scripts. IDesignSpec’s PATENTED technology improves engineer’s productivity and design quality. Check out - https://www.agnisys.com/products/idesignspec-uvm-register-generator/
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