Everything posted by aelms
The usage section of the factory documentation recommends a specific pattern for creating components parameterized by type https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/base/uvm_factory-svh.html#uvm_default_factory.Usage However, uvm_sequence_item::type_name is not defined. Therefore defining a type based on the uvm_sequence_item, following this recommendation will result in a compilation error. I have put together an example illustrating this: https://www.edaplayground.com/x/3N_9 Parameterization on uvm_sequence_item is one example, I would suggest that parameterization on base classes is allowed and they have type_name defined.
aelms posted a topic in UVM (Pre-IEEE) Methodology and BCL Forumuvm_comparer:: compare_field_int() on fields larger than 64 bits silently passes. https://www.edaplayground.com/x/4qDq This is misuse, but silently passing compare is not the best outcome.