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MehulPithva

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  1. That's what my feeling as well that register adapter wont work , need to create seperate predictor model and perform the frontdoor access from it.
  2. I understand what you are saying .. but i have only one transaction of read and write and due to more payload bytes of transaction i need to perform read or write on multiple location , Actually my limitation is in adapter, adapter uvm_reg_bus_op class have only one data filed of register width so if i get more payload (>REG_DATA_WIDTH) in bus2reg or reg2bus for a single read and write transaction ,i do not see the way to update the RAL Model automatically and performing the comparison. I see that with creation of extension class i can manage to send the reg2bus transaction with more than REG_WIDTH payload but i am not sure how can i manage bus2reg method to update the register model
  3. Hi, I am using uvm standard register model , register adapter (bus2reg & reg2bus) to send and receive transaction to ral model and DUT. and it is working fine if i do single read and write.(means i perform the 32 bit read n write using reg.read(status,address,data)reg.write(status,address,data)) My challange is that i have to perform the more than 32 bit transaction which performs the read and write on multiple registers, If there any way to use the same reg.read/write method to perform more than one register
  4. Hi, I am using uvm standard register model , register adapter (bus2reg & reg2bus) to send and receive transaction to ral model and DUT. and it is working fine if i do single read and write.(means i perform the 32 bit read n write using reg.read(status,address,data)reg.write(status,address,data)) My challange is that i have to perform the more than 32 bit transaction which performs the read and write on multiple registers, If there any way to use the same reg.read/write method to perform more than one register it seems your bus2reg implementation would be helpful , if you can share it
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