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kirloy369

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  1. I think that yours issues was fixed in new UVM 1800.2-2017 EDIT Note that UVM do not support 8 bits wide memories mapped into map with 32 bits word when byte addressing is off you will got on 1800.2: KERNEL: UVM_WARNING uvm_reg_map.svh(1558) @ 0: reporter [UVM/REG/ADDR] this version of UVM does not properly support memories with a smaller word width than the enclosing map. map tst_reg_blk.test_reg_map has n_bytes=4 aub=4 while the mem has get_n_bytes 1. multiple memory words fall into one bus address. if that happens memory addressing will be unpacked.
  2. kirloy369

    UVM Override V/s Simulator Compile/Elab

    You cannot reference to "abc" on handle of my_transaction type. Try using $cast as below. begin extended_transaction etx; if($cast(etx,tx)) $display("DEBUG_CODE: IN driver abc = %d",etx.abc); end
  3. kirloy369

    Array Assignment in Sequences

    Try to use: foreach(tx_data_byte) tx_data_byte == data_byte; instead : tx_data_byte == data_byte; I think that operation on whole arrays in constraints is illegal at least when we strictly stick to SV LRM text
  4. Isn't this code from this thread just illegal according to LRM tx_err_bytes == {4,5,7}; unpacked array concatenation may be used only in assignment like context. There is also rule saying that in constraint only integral variables can be used.
  5. vacuous means vacuous pass pass means both vacuous and non-vacous fails So if you use +event+vacuous+pass you are switching off vacous passes and also you switch of all passes as a result all passes are switched off. Command you are using works well. If you would use +event+vacuous+fail you will swotch off vacuous passes and all fails. (there is no vacuous fail)
  6. kirloy369

    RivieraPro bind interface to DUT

    Probably you should contact Aldec's Technical Support or you could use this workaround - try to use binding to module instead binding to instance in your case it would be: bind MyDut whitebox_if wb_if ( sig1, sig2); instead yours: bind dut whitebox_if wb_if ( sig1, sig2); This should helps.
  7. What exactly you want to do? This will disable vacuous pass actions asim +assertaction:off +event+vacuous This will disable all pass actions (vacuous and nonvacuous) asim +assertaction:off +event+pass This will disable all fail action asim +assertaction:off +event+fail This will disable all fail and vacuous pass action asim +assertaction:off +event+fail+vacuous I can just guess that you do not have any assert fail in you design so +assertaction:off +event+pass+vacuous will turn of all action for you, if you'll have any fail then it still would be on +assertaction:off +pass+vacuous will turn of all - as you missed +event which is obligatory do define events on which you want do define on/off. This command is just "+assertaction:off", "+pass+vacuous " is simply ignored
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