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Hongnhattl

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  1. Hi everyone Let me ask a question on how to verify for program/erase suspend and resume operation of a flash memory design? How can I build a master monitor and scoreboard to check for that? Thanks Nhat
  2. Hongnhattl

    UVM Monitor help!!!

    Hi Ruchir, Your answer is a good direction, based on this I know what I need to cover. This is helpful to me. I appreciate that. But one thing I still unclear is that regarding to the data size, as I see on the comment words multi page == 256 x n[2-10], if so the maximum data size of SPI protocol is 10 pages per one transfer. For my DUT, If I want to take larger data size, I need to start multiple read operation. Is that correct? Best regards, Nhat
  3. Hongnhattl

    UVM Monitor help!!!

    Hi Ruchir Thanks for yor help a lot. Thanks to your suggestion, I have found this useful example for reset agent http://forums.accellera.org/files/file/111-cadence-reset-example-and-package/ Let me ask one more question. Iā€‹'m verifying for a read opcode of a SPI memory device DUT. The memory address boundary is from 0 to 0x3FFFFF. The memory is modeled as a file that contains the data pattern for the memory. The address is split into Page address and Byte address, each page has 256 bytes. To read the data, I need to send out the command: one byte opcode + four byte of Address + dummy bytes. The DUT then gets into a continuous read mode, it means it keeps shifting the data output as long as the Chip select signal is still asserted. From this we can see that, the number of data output is however we want. This makes me think a lot how to cover for this. How should I define the coverage point for the number of data output? Besides, Should I verify for every address of the memory and what kind of data pattern I need to cover? Could you and anyone else help me? Thanks and best regards, Nhat ā€‹ā€‹ā€‹
  4. Hongnhattl

    UVM Monitor help!!!

    Thanks all, alot of useful information! Ruchir, the approach about making agents brings me new idea that haven't thought about it, it's helpful information to me. About the reset agent, Do we need to write a scoreboard to check all the signal states whether or not it is reseted? Are there other approaches to check the reset status of the DUT? In my DUT to reset it, I need to send out an opcode instead of controling a reset signal. I made a agent called spi_master to handle sending out all of opcodes, if I make a new reset agent, it seems that I need to reuse the driver from the spi_master agent, i feel something exessive! Could you give me some advice? For enable signal agnets, do we need to write a seperate scoreboard to check for each case? Thanks Nhat
  5. Hongnhattl

    UVM Monitor help!!!

    Hi Tudor Thanks for your reply The below is my code. I think with this code I can only configure mode before the run phase and I don't know how to change the spi_config when the simulation gets into the run phase. How should I change? virtual class spi_base_sequence extends uvm_sequence #(spi_transaction); `uvm_declare_p_sequencer(spi_sequencer) function new(string name="spi_base_seq"); super.new(name); endfunction virtual task pre_body(); if (starting_phase!=null) begin `uvm_info(get_type_name(), $sformatf("%s pre_body() raising %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM); starting_phase.raise_objection(this); end endtask virtual task post_body(); if (starting_phase!=null) begin `uvm_info(get_type_name(), $sformatf("%s post_body() dropping %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM); starting_phase.drop_objection(this); end endtask endclass : spi_base_sequence class spi_seq_req extends spi_base_sequence ; function new(string name = "spi_seq_req"); super.new(name); endfunction : new spi_transaction req; `uvm_object_utils(spi_seq_req) virtual task body(); `uvm_do_with(req, {opcode==8'h03;}) // This seq is transferred by SPI standard `uvm_do_with(req, {opcode==8'h06;}) // Write Enable opcode, transferred by SPI `uvm_do_with(req, {opcode==8'hE8;}) // Select OPI MODE, transferred by SPI `uvm_do_with(req, {opcode==8'h04;}) // After E8 opcode, the subsequence sequences will work with OPI `uvm_do_with(req, {opcode==8'h02;}) // Page Program, transferred by OPI endtask : body endclass: spi_seq_req In spi_test.sv: spi_config cfg =new ; function void build_phase(uvm_phase phase); //Set configure mode for Driver and Monitor mode_t = STR; std_t =SPI; cfg.std_t = std_t; cfg.mode = mode_t; spi_env = spi_env::type_id::create(.name("spi_env"), .parent(this)); uvm_config_db#(uvm_object_wrapper)::set(this,"*.spi_seqr.main_phase", "default_sequence",spi_seq_req::type_id::get());
  6. Hongnhattl

    UVM Monitor help!!!

    Hi Tudor,Your guessing is correct, by default the device work with SPI. To switch modes, spi master needs to send out the opcode to update the registers to configure the device into a certain mode. It turns out that if I want to test the device in OCTA mode, my first seq is to configure the device with OCTA mode by default standard, after that the device turns to work with the updated mode. The problem is that how can we let the SPI agent switch its mode during run time simulation? Can you give me some advice? Thanks Nhat
  7. Hongnhattl

    UVM Monitor help!!!

    Hi Tudor, I have a idea like this, I want to put the mode_t as rand transferred item for sequence, when driver gets this, it will configure for all other components like monitors and slave driver into the same mode as it. Is this possible? If not so, could you give me the relevant way to do that? Thanks Nhat
  8. Hongnhattl

    UVM Monitor help!!!

    Thanks all, alot of useful information! Ruchir, the approach about making agents brings me new idea that haven't thought about it, it's helpful information to me. About the reset agent, Do we need to write a scoreboard to check all the signal states whether or not it is reseted? Are there other approaches to check the reset status of the DUT? In my DUT to reset it, I need to send out an opcode instead of controling a reset signal. I made a agent called spi_master to handle sending out all of opcodes, if I make a new reset agent, it seems that I need to reuse the driver from the spi_master agent, i feel something exessive! Could you give me some advice? For enable signal agnets, do we need to write a seperate scoreboard to check for each case? Thanks Nhat
  9. Hi all, I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up to two interfaces that of SPI Master and Memory. During sending request and reply data, Chip Select Pin (in SPI interface) must go low to enable the transaction. But I don't know how to control this pin when It sends the reply from memory. Because this pin is not an interface of memory slave agent. Could anyone give me some advice? Could I use phases to control the env that has different agents? Thank you, Nhat
  10. Hongnhattl

    UVM Monitor help!!!

    Thanks for your replies, I helped me. By the way, let me ask one more question. The clock in my testbench can run with different frequency, in my spi_top_tb I instantiate a DUT hook up to the interface and then define the clock generation like the below module spi_top_tb; parameter cycle_1 = 3.5; SPI dut(svif); //Clock generation always #cycle_1 svif.SCK_PAD = ~svif.SCK_PAD; ... How can I edit it to make clock cycle become configurable? Thank you and Best regards, Nhat
  11. Hi all, I have a SPI interface, it has three modes to transfer the data out on IO[0:7]. In SPI standard there is just IO[0] is used. QPI mode, it uses IO[3:0] and In OPI mode, the whole IO are used. When driver receives a req from sequencer, it drives that req to the interface depending on modes. The interface sometimes goes with SPI, sometimes QPI or OPI. And I want to monitor the tx data, but I dont't know how to setup the monitor to sample the data corresponding to the mode that the driver has used. Are there ways to make monitor works in the same mode with the driver? Thank you!
  12. Hi all, I have a SPI interface, it has three modes to transfer the data out on IO[0:7]. In SPI standard there is just IO[0] is used. QPI mode, it uses IO[3:0] and In OPI mode, the whole IO are used. When driver receives a req from sequencer, it drives that req to the interface depending on modes. The interface sometimes goes with SPI, sometimes QPI or OPI. And I want to monitor the tx data, but I dont't know how to setup the monitor to sample the data corresponding to the mode that the driver has used. Are there ways to make monitor works in the same mode with the driver? Thank you!
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