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mahbod72

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  1. thanks if i want to initialize counterval to zero that count begin from zero waht can i do?
  2. i want to consider capability to synthesis of sample systemc code whit agility compiler i faced this error aall (E1064) Ports of type sc_bit are not allowed systemc.h Line:324 Col:13 ag_util.h Line:33 Col:12 header.sc.h Line:1075 Col:2 synthesis.sc.cpp Line:6 Col:5 synthesis.sc.cpp Line:3 Col:6
  3. Hi the output is here #include "systemc.h" // define counter SC_MODULE(counter) { sc_in_clk clk; sc_in <bool> clear; sc_out <sc_lv <4> > dout; int countval; void onetwothree(); SC_CTOR(counter) { SC_METHOD(onetwothree); sensitive<<clk.pos(); } }; void counter::onetwothree() { if (clear) countval = 0; else countval++; dout = countval; } /////////////////////// //define dec SC_MODULE (dec_4){ sc_in_clk clk; sc_in< sc_lv<4> > in_d; sc_out< sc_lv<16> > out_d; void process() { if (in_d.read() == "0000") out_d = "0000000000000001"; else if (in_d.read() == "0001") out_d = "0000000000000010"; else if(in_d.read() =="0010") out_d = "0000000000000100"; else if (in_d.read() == "0011") out_d = "0000000000001000"; else if (in_d.read() == "0100") out_d = "0000000000010000"; else if (in_d.read() == "0101") out_d = "0000000000100000"; else if (in_d.read() == "0110") out_d = "0000000001000000"; else if (in_d.read() == "0111") out_d = "0000000010000000"; else if (in_d.read() == "1000") out_d = "0000000100000000"; else if (in_d.read() == "1001") out_d = "0000001000000000"; else if(in_d.read() == "1010") out_d = "0000010000000000"; else if (in_d.read() == "1011") out_d = "0000100000000000"; else if (in_d.read() == "1100") out_d = "0001000000000000"; else if (in_d.read() == "1101") out_d = "0010000000000000"; else if (in_d.read() == "1110") out_d = "0100000000000000"; else if (in_d.read() == "1111") out_d = "1000000000000000"; } SC_CTOR(dec_4) { SC_METHOD(process); sensitive<<clk.pos(); } }; //end define module DEC //define controller SC_MODULE(controller) { sc_in_clk clk; sc_in < sc_lv <16> > T; sc_out < bool > reset_counter; sc_out < sc_logic > ld_ac; sc_out < sc_logic > ld_dr; sc_out < sc_logic > ld_ir; sc_out < sc_logic > ld_tr; sc_out < sc_logic > ld_pc; sc_out < sc_logic > ld_ar; sc_out < sc_logic > ld_ou; sc_out < sc_logic > ld_inp; void process() { ld_dr.write(T.read()[0]); ld_ac.write(T.read()[1]); ld_tr.write(T.read()[2]); ld_ir.write(T.read()[3]); ld_pc.write(T.read()[4]); ld_ar.write(T.read()[5]); ld_ou.write(T.read()[6]); ld_inp.write(T.read()[7]); } SC_CTOR(controller) { SC_METHOD(process,clk.pos()); } }; /////////////////////////////// // define main_controller madul SC_MODULE(main_controller) { sc_in_clk clk; sc_out < sc_logic > ld_ac; sc_out < sc_logic > ld_dr; sc_out < sc_logic > ld_ir; sc_out < sc_logic > ld_tr; sc_out < sc_logic > ld_pc; sc_out < sc_logic > ld_ar; sc_out < sc_logic > ld_ou; sc_out < sc_logic > ld_inp; sc_out <sc_lv <4> > count_out; sc_out <sc_lv <16> > dec_out; sc_signal < sc_lv <16> > T; sc_signal < sc_lv <4> > count2dec; sc_signal < bool > reset_counter; dec_4 *DEC_2; counter *COUNT; controller *CONTROL; void copier() { count_out = count2dec.read(); dec_out = T.read(); } SC_CTOR(main_controller) { SC_METHOD(copier); sensitive << clk; DEC_2 = new dec_4 ("DEC_2"); DEC_2 -> clk(clk); DEC_2 -> in_d(count2dec); DEC_2 -> out_d(T); COUNT = new counter ("COUNT"); COUNT -> clk(clk); COUNT -> clear(reset_counter); COUNT -> dout(count2dec); CONTROL = new controller ("CONTROL"); CONTROL -> clk(clk); CONTROL -> T(T); CONTROL -> reset_counter(reset_counter); CONTROL -> ld_ac(ld_ac); CONTROL -> ld_dr(ld_dr); CONTROL -> ld_ir(ld_ir); CONTROL -> ld_tr(ld_tr); CONTROL -> ld_pc(ld_pc); CONTROL -> ld_ar(ld_ar); CONTROL -> ld_ou(ld_ou); CONTROL -> ld_inp(ld_inp); } }; SC_MODULE(test_bench) { sc_in_clk clk; sc_in < sc_logic > ld_ac; sc_in < sc_logic > ld_dr; sc_in < sc_logic > ld_ir; sc_in < sc_logic > ld_tr; sc_in < sc_logic > ld_pc; sc_in < sc_logic > ld_ar; sc_in < sc_logic > ld_ou; sc_in < sc_logic > ld_inp; //sc_in <sc_lv <16> > count_out; sc_in <sc_lv <4> > count_out; sc_in <sc_lv <16> > dec_out; void process() { } SC_CTOR(test_bench) { SC_CTHREAD(process, clk.pos() ); } }; int sc_main(int argc, char* argv[]) { sc_clock clk; sc_signal < sc_logic > ld_ac; sc_signal < sc_logic > ld_dr; sc_signal < sc_logic > ld_ir; sc_signal < sc_logic > ld_tr; sc_signal < sc_logic > ld_pc; sc_signal < sc_logic > ld_ar; sc_signal < sc_logic > ld_ou; sc_signal < sc_logic > ld_inp; //sc_signal < sc_lv <16> > count_out; sc_signal <sc_lv <4> > count_out; sc_signal <sc_lv <16> > dec_out; main_controller *data_p; test_bench *tb; data_p = new main_controller("data_p"); data_p->clk(clk); data_p->ld_ac(ld_ac); data_p->ld_dr(ld_dr); data_p->ld_ir(ld_ir); data_p->ld_tr(ld_tr); data_p->ld_pc(ld_pc); data_p->ld_ar(ld_ar); data_p->ld_ou(ld_ou); data_p->ld_inp(ld_inp); //data_p->count_out(count_out); data_p->count_out(count_out); data_p->dec_out(dec_out); tb = new test_bench ("testBench"); tb->clk(clk); tb->ld_ac(ld_ac); tb->ld_dr(ld_dr); tb->ld_ir(ld_ir); tb->ld_tr(ld_tr); tb->ld_pc(ld_pc); tb->ld_ar(ld_ar); tb->ld_ou(ld_ou); tb->ld_inp(ld_inp); // tb->count_out(count_out); tb->count_out(count_out); tb->dec_out(dec_out); sc_trace_file *tf; tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd" sc_trace(tf,clk,"clk"); sc_trace(tf, count_out, "count_out"); sc_trace(tf, dec_out, "dec_out"); sc_trace(tf, ld_ac, "ld_ac"); sc_trace(tf, ld_dr, "ld_dr"); sc_trace(tf, ld_ir, "ld_ir"); sc_trace(tf, ld_tr, "ld_tr"); sc_trace(tf, ld_pc, "ld_pc"); sc_trace(tf, ld_ar, "ld_ar"); sc_trace(tf, ld_ou, "ld_ou"); sc_trace(tf, ld_inp, "ld_inp"); sc_start(50); sc_close_vcd_trace_file(tf); return 0; }
  4. if i use wait and while i get a reasonable response but if i use SC_METHOD get wrong response. and the counter not work. i dont know!
  5. mahbod72

    wait()

    are wait() capable to synthesis in systemc?
  6. Hi i want to manage the flow of the out put ports of the main controller (see figure) for this goal i design a counter and connect it to the decoder the out put of the decoder is T[0] to T[15] for example the order of the ports as follow but this idea is not work ld_dr.write(T.read()[0]); ld_ac.write(T.read()[1]); ld_tr.write(T.read()[2]); ld_ir.write(T.read()[3]); ld_pc.write(T.read()[4]); ld_ar.write(T.read()[5]); ld_ou.write(T.read()[6]); ld_inp.write(T.read()[7]); the code is here #include "systemc.h" // define counter SC_MODULE(counter) { sc_in_clk clk; sc_in <bool> clear; sc_out <sc_lv <4> > dout; int countval; void onetwothree(); SC_CTOR(counter) { SC_METHOD(onetwothree); sensitive<<clk.pos(); } }; void counter::onetwothree() { if (clear) countval = 0; else countval++; dout = countval; } /////////////////////// //define dec SC_MODULE (dec_4){ sc_in_clk clk; sc_in< sc_lv<4> > in_d; sc_out< sc_lv<16> > out_d; void process() { if (in_d.read() == "0000") out_d = "0000000000000001"; else if (in_d.read() == "0001") out_d = "0000000000000010"; else if(in_d.read() =="0010") out_d = "0000000000000100"; else if (in_d.read() == "0011") out_d = "0000000000001000"; else if (in_d.read() == "0100") out_d = "0000000000010000"; else if (in_d.read() == "0101") out_d = "0000000000100000"; else if (in_d.read() == "0110") out_d = "0000000001000000"; else if (in_d.read() == "0111") out_d = "0000000010000000"; else if (in_d.read() == "1000") out_d = "0000000100000000"; else if (in_d.read() == "1001") out_d = "0000001000000000"; else if(in_d.read() == "1010") out_d = "0000010000000000"; else if (in_d.read() == "1011") out_d = "0000100000000000"; else if (in_d.read() == "1100") out_d = "0001000000000000"; else if (in_d.read() == "1101") out_d = "0010000000000000"; else if (in_d.read() == "1110") out_d = "0100000000000000"; else if (in_d.read() == "1111") out_d = "1000000000000000"; } SC_CTOR(dec_4) { SC_METHOD(process); sensitive<<clk.pos(); } }; //end define module DEC //define controller SC_MODULE(controller) { sc_in_clk clk; sc_in < sc_lv <16> > T; sc_out < bool > reset_counter; sc_out < sc_logic > ld_ac; sc_out < sc_logic > ld_dr; sc_out < sc_logic > ld_ir; sc_out < sc_logic > ld_tr; sc_out < sc_logic > ld_pc; sc_out < sc_logic > ld_ar; sc_out < sc_logic > ld_ou; sc_out < sc_logic > ld_inp; void process() { ld_dr.write(T.read()[0]); ld_ac.write(T.read()[1]); ld_tr.write(T.read()[2]); ld_ir.write(T.read()[3]); ld_pc.write(T.read()[4]); ld_ar.write(T.read()[5]); ld_ou.write(T.read()[6]); ld_inp.write(T.read()[7]); } SC_CTOR(controller) { SC_CTHREAD(process,clk.pos()); } }; /////////////////////////////// // define main_controller madul SC_MODULE(main_controller) { sc_in_clk clk; sc_out < sc_logic > ld_ac; sc_out < sc_logic > ld_dr; sc_out < sc_logic > ld_ir; sc_out < sc_logic > ld_tr; sc_out < sc_logic > ld_pc; sc_out < sc_logic > ld_ar; sc_out < sc_logic > ld_ou; sc_out < sc_logic > ld_inp; sc_out <sc_lv <4> > count_out; sc_out <sc_lv <16> > dec_out; sc_signal < sc_lv <16> > T; sc_signal < sc_lv <4> > count2dec; sc_signal < bool > reset_counter; dec_4 *DEC_2; counter *COUNT; controller *CONTROL; void copier() { count_out = count2dec.read(); dec_out = T.read(); } SC_CTOR(main_controller) { SC_METHOD(copier); sensitive << clk; DEC_2 = new dec_4 ("DEC_2"); DEC_2 -> clk(clk); DEC_2 -> in_d(count2dec); DEC_2 -> out_d(T); COUNT = new counter ("COUNT"); COUNT -> clk(clk); COUNT -> clear(reset_counter); COUNT -> dout(count2dec); CONTROL = new controller ("CONTROL"); CONTROL -> clk(clk); CONTROL -> T(T); CONTROL -> reset_counter(reset_counter); CONTROL -> ld_ac(ld_ac); CONTROL -> ld_dr(ld_dr); CONTROL -> ld_ir(ld_ir); CONTROL -> ld_tr(ld_tr); CONTROL -> ld_pc(ld_pc); CONTROL -> ld_ar(ld_ar); CONTROL -> ld_ou(ld_ou); CONTROL -> ld_inp(ld_inp); } }; SC_MODULE(test_bench) { sc_in_clk clk; sc_in < sc_logic > ld_ac; sc_in < sc_logic > ld_dr; sc_in < sc_logic > ld_ir; sc_in < sc_logic > ld_tr; sc_in < sc_logic > ld_pc; sc_in < sc_logic > ld_ar; sc_in < sc_logic > ld_ou; sc_in < sc_logic > ld_inp; //sc_in <sc_lv <16> > count_out; sc_in <sc_lv <4> > count_out; sc_in <sc_lv <16> > dec_out; void process() { } SC_CTOR(test_bench) { SC_CTHREAD(process, clk.pos() ); } }; int sc_main(int argc, char* argv[]) { sc_clock clk; sc_signal < sc_logic > ld_ac; sc_signal < sc_logic > ld_dr; sc_signal < sc_logic > ld_ir; sc_signal < sc_logic > ld_tr; sc_signal < sc_logic > ld_pc; sc_signal < sc_logic > ld_ar; sc_signal < sc_logic > ld_ou; sc_signal < sc_logic > ld_inp; //sc_signal < sc_lv <16> > count_out; sc_signal <sc_lv <4> > count_out; sc_signal <sc_lv <16> > dec_out; main_controller *data_p; test_bench *tb; data_p = new main_controller("data_p"); data_p->clk(clk); data_p->ld_ac(ld_ac); data_p->ld_dr(ld_dr); data_p->ld_ir(ld_ir); data_p->ld_tr(ld_tr); data_p->ld_pc(ld_pc); data_p->ld_ar(ld_ar); data_p->ld_ou(ld_ou); data_p->ld_inp(ld_inp); //data_p->count_out(count_out); data_p->count_out(count_out); data_p->dec_out(dec_out); tb = new test_bench ("testBench"); tb->clk(clk); tb->ld_ac(ld_ac); tb->ld_dr(ld_dr); tb->ld_ir(ld_ir); tb->ld_tr(ld_tr); tb->ld_pc(ld_pc); tb->ld_ar(ld_ar); tb->ld_ou(ld_ou); tb->ld_inp(ld_inp); // tb->count_out(count_out); tb->count_out(count_out); tb->dec_out(dec_out); sc_trace_file *tf; tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd" sc_trace(tf,clk,"clk"); sc_trace(tf, count_out, "count_out"); sc_trace(tf, dec_out, "dec_out"); sc_trace(tf, ld_ac, "ld_ac"); sc_trace(tf, ld_dr, "ld_dr"); sc_trace(tf, ld_ir, "ld_ir"); sc_trace(tf, ld_tr, "ld_tr"); sc_trace(tf, ld_pc, "ld_pc"); sc_trace(tf, ld_ar, "ld_ar"); sc_trace(tf, ld_ou, "ld_ou"); sc_trace(tf, ld_inp, "ld_inp"); sc_start(50); sc_close_vcd_trace_file(tf); return 0; }
  7. yes i forgot i must to insert this thak you SC_METHOD(process); sensitive<<bus;
  8. good point sc_unit() is better i use this and problem is solved tank you sc_lv<12> addr_lv = addr.read(); sc_uint<12> add = addr_lv; out1 = ram_data[add]; if(clk){ if (ld) { ram_data[add] = in1; }
  9. Hi i write this sample code in this code i connect two register i want to trace bus_out signal that is between two register with VCD view but in VCD view the value of bus_out signal is xxxx while bus_out must be value! the image of VCD is attached // mahbod #include "systemc.h" // define reg 16 bit SC_MODULE (reg16bit) { sc_in <bool> inc,ld,clr; sc_in <sc_lv <16> > in16; sc_out <sc_lv <16> > out16; sc_in <bool> clk; void reg_func (); SC_CTOR (reg16bit) { SC_THREAD (reg_func); sensitive << clk.pos(); } }; // define reg function void reg16bit::reg_func () { while (1) { if (ld) out16 = in16; if (clr) out16 = "0000000000000000"; if(inc) out16 = (sc_lv <16>)(out16.read().to_int()+1); wait (); } } //end define reg 16 bit // defination data path madule SC_MODULE(data_path) { sc_in_clk clk; sc_in < sc_lv <16> > inp; sc_in < bool > ld_ac; sc_in < bool > inc_ac; sc_in < bool > clr_ac; sc_in < bool > ld_inp; sc_in < bool > inc_inp; sc_in < bool > clr_inp; sc_out < sc_lv <16> > outp; sc_out < sc_lv <16> > bus_out; sc_signal< sc_lv <16> > bus; reg16bit *AC; reg16bit *INP; void process() { bus_out = bus.read(); } SC_CTOR(data_path) { AC = new reg16bit ("AC"); AC->inc(inc_ac); AC->ld(ld_ac); AC->clr(clr_ac); AC->in16(bus); AC->out16(outp); AC->clk(clk); INP = new reg16bit ("INP"); INP->inc(inc_inp); INP->ld(ld_inp); INP->clr(clr_inp); INP->in16(inp); INP->out16(bus); INP->clk(clk); } }; SC_MODULE(test_bench) { sc_in_clk clk; sc_out < sc_lv <16> > inp; sc_out < bool > ld_ac; sc_out < bool > inc_ac; sc_out < bool > clr_ac; sc_out < bool > ld_inp; sc_out < bool > inc_inp; sc_out < bool > clr_inp; sc_in < sc_lv <16> > outp; sc_in < sc_lv <16> > bus_out; void process() { while(1) { inp = (sc_lv <16>) "0000000000000110"; wait(); ld_inp = (bool) 1; wait(); ld_inp = (bool) 0; wait(); ld_ac = (bool) 1; wait(); ld_ac = (bool) 0; wait(); inc_ac = (bool) 1; wait(); inc_ac = (bool) 0; wait(); } } SC_CTOR(test_bench) { SC_CTHREAD(process, clk.pos() ); } }; int sc_main(int argc, char* argv[]) { sc_clock clk; sc_signal < sc_lv <16> > inp; sc_signal < bool > ld_ac; sc_signal < bool > inc_ac; sc_signal < bool > clr_ac; sc_signal < bool > ld_inp; sc_signal < bool > inc_inp; sc_signal < bool > clr_inp; sc_signal < sc_lv <16> > outp; sc_signal < sc_lv <16> > bus_out; data_path *data_p; test_bench *tb; data_p = new data_path("data_p"); data_p->clk(clk); data_p->inp(inp); data_p->ld_ac(ld_ac); data_p->inc_ac(inc_ac); data_p->clr_ac(clr_ac); data_p->ld_inp(ld_inp); data_p->inc_inp(inc_inp); data_p->clr_inp(clr_inp); data_p->outp(outp); data_p->bus_out(bus_out); tb = new test_bench ("testBench"); tb->clk(clk); tb->inp(inp); tb->ld_ac(ld_ac); tb->inc_ac(inc_ac); tb->clr_ac(clr_ac); tb->ld_inp(ld_inp); tb->inc_inp(inc_inp); tb->clr_inp(clr_inp); tb->outp(outp); tb->bus_out(bus_out); sc_trace_file *tf; tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd" sc_trace(tf,clk,"clk"); sc_trace(tf,inp,"inp"); sc_trace(tf,outp,"outp"); sc_trace(tf,ld_ac,"ld_ac"); sc_trace(tf,ld_inp,"ld_inp"); sc_trace(tf,inc_ac,"inc_ac"); sc_trace(tf,inc_inp,"inc_inp"); sc_trace(tf,clr_ac,"clr_ac"); sc_trace(tf,clr_inp,"clr_inp"); sc_trace(tf,bus_out,"bus_out"); sc_start(100); sc_close_vcd_trace_file(tf); return 0; }
  10. Hi is this memory definition is true? SC_MODULE(mem16) { sc_in <sc_lv <16> > in1; sc_out <sc_lv <16> > out1; sc_in <sc_lv <12> > addr; sc_in <bool> ld; sc_in_clk clk; int i; void write_data(); sc_lv <16> ram_data[4096]; SC_CTOR(mem16) { SC_METHOD(write_data); sensitive << addr << ld << in1 << clk ; //memory initialization ram_data[0]="0000000000000001"; ram_data[1]="0000000000000011"; ram_data[2]="0000000000000111"; ram_data[3]="0000000000001111"; ram_data[4]="0000000000011111"; ram_data[5]="0000000000111111"; ram_data[6]="0000000001111111"; //for (i=7; i++; i<4095) //ram_data[i] = 0; } }; void mem16::write_data() { out1 = ram_data[addr.read().to_int()]; if(clk){ if (ld) { ram_data[addr.read().to_int()] = in1; } } }
  11. Hi i study about softwares that suport systemc in simuation or synthesis. for example c to silicon compiler from cadene. but when i study datasheet of these softwares ,i cant understand some of the features that in these datasheets. i searching the document that explain this features very good but i cant find it. please help
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