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Luis.Cargnini

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  1. Thanks David,, I f using sc_spawn, ca I ahve multiple threads drivng a vector signal ? Because this is my main problem, currently. I have a process 0 that writes in vector[0] and process1 in vector[1], during simulation if raises a flag tha ttwo separated methods are trying to drive teh same signal, it is thea sam signal but not in the same position. I tried to fix that using 'consolidation approach' as explained in "a systemC Primer" page 135, but now I had the same problem. So now I'm trying the sc_spawn, but I'm not finding the way to use sc_spawn_options to set the sensitive list of the spawned process in the main process. Any links for examples ?
  2. Thanks Alan, In HDL I would place this in separated process (different signals) and use a last process to unify, everything, or place this multiple process as one process and, since pretty much everyone is in a different channel. I was trying with for() interactions, but the problem is I have to test them independently not sequentially. Do you know if there is a way to have threads inside of a process ? this would make more sense than splitting into different process (in HDL would occur concurrence) in SystemC I'm not sure if things will happen sequentially, locking the entire processes flow in any given moment, especially in the following test: if(_bufferOut_busyIn[*].read() == false){ ...... } This line is the reason why I broke into multiple processes to avoid starvation in any interface with data while some may not have, and to control the flow of the ack signals. Also, could I wrote some code like : SwitchFabric:::SwitchFabric(){ SC_METHOD(sendDatasAcrossQueues) sensitive << rstn; sensitive clk.pos(); } ... void SwitchFabric::sendDatasAcrossQueues(){ SC_THREAD(sendDataQueues0); sensitive << rstn; sensitive clk.pos(); SC_THREAD(sendDataQueues1); sensitive << rstn; sensitive clk.pos(); SC_THREAD(sendDataQueues1); sensitive << rstn; sensitive clk.pos(); SC_THREAD(sendDataQueues1); sensitive << rstn; sensitive clk.pos(); } Regards Vitorio.
  3. Hello, I'm trying to model a packet switcher, for such I broke the packet assignment of different ports in different methods, because I need to evaluate each port in parallel, however the system complains of multiple access at the same signal. To try to avoid this, before execution, I had a sc_mutex placed, but it didn't seem to have worked, my code follows the following ruleset (I'll copy only two methods to avoid long threads): enum sqstate_t {SQINIT,SQIDLE,LRS0,LRS1, LRS2,LRS2N,LRS2S,LRS2W,LRS2E}; sc_signal < sqstate_t > sqControlQ0; sc_signal < sqstate_t > sqControlQ1; sc_mutex _qmux; void SwitchFabric::sendDataQueues0(){ Packet _temp; if(rstn.read() == false){ if(_qmux.trylock() > 0){ _bufferIn_read[0].write(false); _bufferOut_write[0].write(false); _qmux.unlock(); } sqControlQ0 = SQINIT; } else{ //TODO: Working to transform it into a FSM /** * Cycle across multiple queues */ switch(sqControlQ0){ case SQINIT: _bufferIn_read[0].write(false); _bufferOut_write[0].write(false); sqControlQ = SQIDLE; break; case SQIDLE: //for(int i = 0; i < _NPORTS; i++){ if(_bufferIn_busyOut[0].read() != false){ _temp = _inpktOut[0].read(); _bufferIn_read[0].write(true); sqControlQ0 = LRS0; } else{ _bufferIn_read[0].write(false); sqControlQ0 = SQIDLE; } //} break; case LRS0: _bufferIn_read[0].write(false); sqControlQ0 = LRS1; break; case LRS1: if(addressing_logic){ if(_bufferOut_busyIn[1].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[1].write(_temp); _bufferOut_write[1].write(true); //_qmux.unlock(); sqControlQ0 = LRS2S; } else{ sqControlQ0 = LRS1; } } else{ sqControlQ0 = LRS1; } } else { if(_bufferOut_busyIn[3].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[3].write(_temp); _bufferOut_write[3].write(true); //_qmux.unlock(); sqControlQ0 = LRS2E; } else{ sqControlQ0 = LRS1; } } else{ sqControlQ0 = LRS1; } } } else{ if(addressing_logic){ if(_bufferOut_busyIn[2].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[2].write(_temp); _bufferOut_write[2].write(true); //_qmux.unlock(); sqControlQ0 = LRS2W; } else{ sqControlQ0 = LRS1; } } else{ sqControlQ0 = LRS1; } } else { if(_bufferOut_busyIn[0].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[0].write(_temp); _bufferOut_write[0].write(true); //_qmux.unlock(); sqControlQ0 = LRS2N; } else{ sqControlQ0 = LRS1; } } else{ sqControlQ0 = LRS1; } } } break; case LRS2N: _bufferOut_write[0].write(false); _qmux.unlock(); sqControlQ0 = SQIDLE; //TODO: or maybe some other state break; case LRS2S: _bufferOut_write[1].write(false); _qmux.unlock(); sqControlQ0 = SQIDLE; //TODO: or maybe some other state break; case LRS2W: _bufferOut_write[2].write(true); _qmux.unlock(); sqControlQ0 = SQIDLE; //TODO: or maybe some other state break; case LRS2E: _bufferOut_write[3].write(true); _qmux.unlock(); sqControlQ0 = SQIDLE; //TODO: or maybe some other state break; default: break; } } } void SwitchFabric::sendDataQueues1(){ Packet _temp; if(rstn.read() == false){ if(_qmux.trylock() > 0){ _bufferIn_read[1].write(false); _bufferOut_write[1].write(false); _qmux.unlock(); } sqControlQ1 = SQINIT; } else{ //TODO: Working to transform it into a FSM /** * Cycle across multiple queues */ switch(sqControlQ1){ case SQINIT: //for(int i = 0; i < _NPORTS; i++){ _bufferIn_read[1].write(false); _bufferOut_write[1].write(false); //} sqControlQ = SQIDLE; break; case SQIDLE: //for(int i = 0; i < _NPORTS; i++){ if(_bufferIn_busyOut[1].read() != false){ _temp = _inpktOut[1].read(); _bufferIn_read[1].write(true); sqControlQ1 = LRS0; } else{ _bufferIn_read[1].write(false); sqControlQ1 = SQIDLE; } //} break; case LRS0: _bufferIn_read[1].write(false); sqControlQ1 = LRS1; break; case LRS1: if(Adressing_logic){ if(_bufferOut_busyIn[1].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[1].write(_temp); _bufferOut_write[1].write(true); //_qmux.unlock(); sqControlQ1 = LRS2S; } else{ sqControlQ1 = LRS1; } } else{ sqControlQ1 = LRS1; } } else { if(_bufferOut_busyIn[3].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[3].write(_temp); _bufferOut_write[3].write(true); //_qmux.unlock(); sqControlQ1 = LRS2E; } else{ sqControlQ1 = LRS1; } } else{ sqControlQ1 = LRS1; } } } else{ if(Adressing_logic2) ){ //this->_bufferOut[1].dataIn = _temp; if(_bufferOut_busyIn[2].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[2].write(_temp); _bufferOut_write[2].write(true); //_qmux.unlock(); sqControlQ1 = LRS2W; } else{ sqControlQ1 = LRS1; } } else{ sqControlQ1 = LRS1; } } else { if(_bufferOut_busyIn[0].read() == false){ if(_qmux.trylock() > 0){ _outpktIn[0].write(_temp); _bufferOut_write[0].write(true); //_qmux.unlock(); sqControlQ1 = LRS2N; } else{ sqControlQ1 = LRS1; } } else{ sqControlQ1 = LRS1; } } } break; case LRS2N: _bufferOut_write[0].write(false); _qmux.unlock(); sqControlQ1 = SQIDLE; //TODO: or maybe some other state break; case LRS2S: _bufferOut_write[1].write(false); _qmux.unlock(); sqControlQ1 = SQIDLE; //TODO: or maybe some other state break; case LRS2W: _bufferOut_write[2].write(true); _qmux.unlock(); sqControlQ1 = SQIDLE; //TODO: or maybe some other state break; case LRS2E: _bufferOut_write[3].write(true); _qmux.unlock(); sqControlQ1 = SQIDLE; //TODO: or maybe some other state break; default: break; } } } Please, if anyone could advise me on how to proceed to have this as parallel process in any way, even if I have to t everything in the same process, but working as Threads I would appreciate it. P.S.: I saw in the internet people saying to use export SC_SIGNAL_WRITE_CHECK=DISABLE, and the problem disappear, it may disappear, but I'm not sure if this is the right fix in this case.
  4. Luis.Cargnini

    Problems with custom Packet Class in sc_in/sc_out

    Thank you all for the assistance, I solved the problem following your recommendations. Thanks for your time.
  5. Luis.Cargnini

    Problems with custom Packet Class in sc_in/sc_out

    Thanks again @dakupoto: Why not unsigned: in fact sc_bv seems more RTL oriented, this way, is my understanding, that I can keep the coherence between my SystemC model and my later RTL implementation, using the SystemC as golden model, for the implementation. Also the 'Packet' resembles a user defined type in VHDL as well in SystemVerilog (struct), also in verilog I would only have to break the class into separated in/out signals or a single bit vector and remap internally into the module for organization purposes. In addition to that, using elementary types like sc_bv this mandates me to use binary operations only, since according with the description you cannot operate with this values, without relying in a 'a=b/c' in C++ for example, avoiding anyone in the future doing that, once they use this model to try and experiment with it. That makes sense to you ? About the inheritance of the sc_sginal: OK I'll avoid it completely to not mask any mistake underneath my implementation in C++
  6. Luis.Cargnini

    Problems with custom Packet Class in sc_in/sc_out

    So thank everyone for the help, now I saw what you all meant, the Packet in the main.cpp, I changed and it compiled. But answering: by extend I meant : Inherit the class signal into class Packet, would that be possible ? or just overload the necessary operators ? How to exaclty find them, the ones I need to overload ? However, when I tried to execute, after fixing with the sc_signal, I got the error message below: Error: (E109) complete binding failed: port not bound: port 'UUT.port_9' (sc_out) In file: ../../../../src/sysc/communication/sc_port.cpp:231 my new main.cpp is the following: int _channel = 0; sc_clock clk("clk",10,SC_NS, 0.5); //sc_reset rstn("rstn", 0 , SC_NS, 2.0); sc_signal< bool > rstn;// = rstn; sc_signal<bool> _run; sc_sgnal< Packet > pkt1, pkt2; Packet tpkt1, tpkt2; tpkt1._field1= 0x0000; tpkt1._field1 = 0x0001; tpkt1._index = 0x0000; tpkt1._data = 0Xffff; _run.write(true); pkt1.write(tpkt1); Queue tqueue("UUT"); tqueue.clk(clk); tqueue.clkin(clk); tqueue.clkout(clk); tqueue.rstn(rstn); tqueue.dataIn(pkt1); tqueue.dataOut(pkt2); tqueue.write(_run); tqueue.read(_run); tpkt2 = pkt2.read(); sc_start(); return EXIT_SUCCESS; Off-Topic: Besides there is a better debugger for C++ then DDD ? specially using Clang++ ? I tried to debug but was quite complicated to 'see' anything. Regards, Vitorio.
  7. Luis.Cargnini

    Problems with custom Packet Class in sc_in/sc_out

    So Should I 'extend' sc_signal in my class so I can use it in a sc_in or sc_out port of a major device ? O I should reduce my expectaion and use a sc_bv<n> of the size I want and remap everytime in each class I exchange the packet ? Vitorio.
  8. Hello, I have a Packet class, that for the last week I had to overload some operators ot make it compile using SystemC. Currently I'm trying to instantiate this class in the main file to start testing and I am having compilation issues. The custom class: from my_defines.h typedef sc_bv< _DATA_SIZE > particle_t; #include <systemc.h> #include "my_defines.h" class Packet { public: sc_bv< _BITADDR > _field1; sc_bv< _BITADDR > _field2; sc_bv< _INDEX > _index; particle_t _data; virtual ~Packet(); Packet(); Packet(sc_bv<_BITADDR> _field1, sc_bv< _BITADDR > _field2 sc_bv< _INDEX > _index, particle_t _data); .... } inline Packet& operator =(const Packet& rhs){ ... } inline friend void sc_trace(sc_trace_file *tf, const Packet & v, const std::string & NAME ){ .... } inline friend ostream& operator<<(ostream& os, Packet const & v) { .... } }; Queue: SC_MODULE(Queue) { sc_in< bool > rstn; sc_in< bool > clk; // ??? keep it or remove it ? //P1 sc_in< bool > clkin; sc_in< bool > write; sc_in< Packet > dataIn; sc_out< bool > busyIn; //P2 sc_in< bool > clkout; sc_in< bool > read; sc_out< Packet > dataOut; sc_out< bool > busyOut; // wait is a reserved word so I used busy for now //public: sc_fifo< Packet > *_buffer;//(_BUFFER_SIZE); //they key component Main file: ... int sc_main(int argc, char *argv[]) { int _channel = 0; sc_clock clk("clk",10,SC_NS, 0.5); //sc_reset rstn("rstn", 0 , SC_NS, 2.0); sc_signal< bool > rstn;// = rstn; sc_signal<bool> enable; Packet pkt1, pkt2; pkt1._field1= 0x0000; pkt1._field1 = 0x0001; pkt1._index = 0x0000; pkt1._data = 0Xffff; Queue tqueue("UUT"); tqueue.clk(clk); tqueue.clkin(clk); tqueue.clkout(clk); tqueue.rstn(rstn); tqueue.dataIn(pkt1); tqueue.dataOut(pkt2); tqueue.write(true); tqueue.read(true); sc_start(); return EXIT_SUCCESS; } Whe I coimpile Queue and Packet it compiles without problems, but when I try to compile the main file I'm receiving the error messages below. I'm using clang++ and the systemc was compiled with clang++ too, so if anyone could give me a help I would appreciate it since SystemC is not exactly 'my cup of tea' and I'm begiinig with it. ERROR LOG: clang++ -I. -I.. -I/opt/vlsi/systemc/include -c src/systemc/packet.cpp -o src/systemc/packet.o clang++ -I. -I.. -I/opt/vlsi/systemc/include -c src/systemc/queue.cpp -o src/systemc/queue.o clang++ -I. -I.. -I/opt/vlsi/systemc/include -c src/systemc/main.cpp -o src/systemc/main.o src/systemc/main.cpp:43:2: error: no matching function for call to object of type 'sc_in<Packet>' tqueue.dataIn(pkt1); ^~~~~~~~~~~~~ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:166:10: note: candidate function not viable: no known conversion from 'Packet' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument void operator () ( const in_if_type& interface_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:175:10: note: candidate function not viable: no known conversion from 'Packet' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( in_port_type& parent_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:184:10: note: candidate function not viable: no known conversion from 'Packet' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( inout_port_type& parent_ ) ^ src/systemc/main.cpp:44:2: error: no matching function for call to object of type 'sc_out<Packet>' tqueue.dataOut(pkt2); ^~~~~~~~~~~~~~ /opt/vlsi/systemc/include/sysc/communication/sc_port.h:270:10: note: candidate function not viable: no known conversion from 'Packet' to 'sc_core::sc_signal_inout_if<Packet> &' for 1st argument void operator () ( IF& interface_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_port.h:279:10: note: candidate function not viable: no known conversion from 'Packet' to 'port_type &' (aka 'sc_port_b<sc_core::sc_signal_inout_if<Packet> > &') for 1st argument void operator () ( port_type& parent_ ) ^ src/systemc/main.cpp:45:2: error: no matching function for call to object of type 'sc_in<bool>' tqueue.write(true); ^~~~~~~~~~~~ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:489:10: note: candidate function not viable: no known conversion from 'bool' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument void operator () ( const in_if_type& interface_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:498:10: note: candidate function not viable: no known conversion from 'bool' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( in_port_type& parent_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:507:10: note: candidate function not viable: no known conversion from 'bool' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( inout_port_type& parent_ ) ^ src/systemc/main.cpp:46:2: error: no matching function for call to object of type 'sc_in<bool>' tqueue.read(true); ^~~~~~~~~~~ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:489:10: note: candidate function not viable: no known conversion from 'bool' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument void operator () ( const in_if_type& interface_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:498:10: note: candidate function not viable: no known conversion from 'bool' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( in_port_type& parent_ ) ^ /opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:507:10: note: candidate function not viable: no known conversion from 'bool' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument void operator () ( inout_port_type& parent_ ) ^ 4 errors generated.
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