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assafgedalia

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  1. Alan you are the man! there was a rogue cfg in the transaction i created, and now i understand that the scope of the constraint is the scope of the new transaction and in the scope of the newly created transaction the cfg has not been declared yet. many thanks, Assaf
  2. Hi, i have an agent (uvm_agent) which has a config object (uvm_object) which holds the agent's configurations. i am setting this config from the environment and getting it inside the agent. in the agent i am setting this config for everyone to see (*). i have a sequence for this object that get's this config object. everything works ok so far and i am able to access all the configurations from the config object inside the sequence. the problem starts when i try to create constrained transactions (`uvm_do_with) with the constraints taken from this config object. then i get a null pointer error. the error: Error-[CNST-NPE] Constraint null pointer error /space/users/assafg/nu4000/verification/iae/ciif_agent/ciif_sequence.sv, 194 Accessing null pointer cfg.frame_width in constraints. Please make sure variable cfg.frame_width is allocated. so i can access a certain field from the sequence but when i try to set it as a constraint i get an error. some code from the sequence (this is only part of the code): virtual task pre_start(); // Get the configuration if (!uvm_config_db #(ciif_cfg)::get(get_sequencer(), "", "cfg", cfg)) begin `uvm_fatal("CFGERR", "%m cfg not set") end endtask: pre_start virtual task body(); `uvm_info("DEBUG_DEBUG", $sformatf("cfg.frame_width = %0d\n", cfg.frame_width), UVM_NONE); // print occurs and proves that i can access this field `uvm_do_with(req, { fwidth == cfg.frame_width; // error here } ); endtask: body any idea would be much appreciated. Thanks, Assaf
  3. Hi, fr some strange reason everything i try to randomize() returns constant values. it's not that the randomization fails (i check the returned response) but instead it just remains with the original value. has this ever happened to anyone? any idea why? many thanks, Assaf
  4. Hi, can i use uvm_config_db::get function from inside a module? i want to create a configuration object in the test, set it at the config_db and get it in a VIP written as a module. something like this: module vip(); initial begin // Wait for first clock - this means we are in the main phase @(posedge if.clk); if (!uvm_config_db#(vip_config)::get(null, "uvm_test_top","cfg", cfg)) begin `uvm_fatal("CFGERR", "%m vip cfg not set") end ... end endmodule i tried this and got the fatal error, meaning the cfg wasn't found. i tried instead to create a typedef struct and pass it from the test to the module using set and get but the simulation crashed - "--- Stack trace follows". Any help would be much appreciated. Thx, Assaf
  5. Thanks for the answer. i'm using a VIP that is `protected so i don't have access to the driver. all i can do is create a sequence and "feed" it to the driver, inside the sequence i use the code i attached in my previous post. (the case is there because there is also a write option which i omitted) isn't the transaction deleted at the end of the uvm_do_with? otherwise can i use something like this: class sequence; int data; virtual task body(); apb_item#(AW, DW) it; `uvm_do_with(it, { it.address == tr_address; it.rw == op_kind; } );// `uvm_do_with this.data = it.data; endtask: body endclass and then read it from the higher hierarchy the creates the sequence and "feeds" it to the driver? Thx, Assaf
  6. Hello, let's say i have a sequence, in this sequence i'm reading data using the uvm_do_with macro. an example would be a read transaction in an APB agent. how do i extract the data from it? PARTIAL CODE: virtual task body(); apb_item#(AW, DW) it; case(op_kind) `APB_READ: begin `uvm_do_with(it, { it.address == tr_address; it.rw == op_kind; } );// `uvm_do_with end endcase endtask: body Thx, Assaf
  7. assafgedalia

    cloning a register

    thanks for your response. the problem with this approach is that i want to do it automatically (foreach registers...) and each register has different fields so i won't know how exactly to store the values. i could save: a value, how many fields, the size of each field etc. but it creates a lot of code... there must be an easy way to create a copy of a register... Thx, Assaf
  8. Hello, I am running a simulation on a DUT that has a register model. what i wish to do is hold a copy of that register model so that at certain times during the simulation i can compare a current value of a register to a former value of that register taken at a previous point in time. i don't want to save only the data of the registers, but an array of registers that will hold a copy of the whole register object, including all of it's fields and other attributes. i tried to create an array of type uvm_reg uvm_reg registers_copy[] and then use clone to copy a register to that array $cast(registers_copy, registers.clone()); but i get an error: UVM_FATAL /tools/snps/vcs/current/etc/uvm-1.1/reg/uvm_reg.svh(3102) @ 3520.6ns: reporter [RegModel] RegModel registers cannot be cloned how can i create a copy of my register model at certain points in time? Thanks for your help, Assaf
  9. assafgedalia

    problem with uvm ral read/mirror

    I Understand now what you meant, i fixed the driver to handle the read correctly and it solved the problem. Thanks.
  10. assafgedalia

    problem with uvm ral read/mirror

    Tudor, there is no place in my monitor code where i call bus2reg, is it done implicitly somewhere? if this is indeed the case, and if i understand you correctly, one of these bus2reg calls is done incorrectly? so how exactly do i fix this issue? what exactly do you mean by "updating the response item for reads inside the driver with the appropriate data" ? i tried to look up some examples for the sequencer-driver communication and all the examples i see look something like this: seq_item_port.get_next_item(req); rsp = apb_transaction::type_id::create("rsp", this); rsp.set_id_info(req); // Flag item done seq_item_port.item_done(); seq_item_port.put_response(rsp); i tried to add this code to my driver but it did not solve my problem. more help would be much appreciated Thx, Assaf
  11. Hi, I am having some trouble with creating a register model for my DUT. It is intended for APB transactions. I included an adapter and a predictor. When i try to read or mirror a register i have written to i get a wrong value. when looking at the waves i see that ALL my transactions are done properly - read and write. also i noticed that the bus2reg function is called twice for each transaction, and in the write transactions both calls to bus2reg function gives the same values but in the read transaction, the first call to bus2reg is good and in the second call i get 0 in the data. Any thoughts would be much appreciated... my adapter: virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); apb_transaction tr; `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH); if (!$cast(tr, bus_item)) begin `uvm_fatal("REGERR", "%m: Failed to convert bus2reg"); end rw.addr = tr.addr; rw.data = tr.data; rw.kind = tr.op_kind; rw.status = UVM_IS_OK; `uvm_info("DEBUG", $sformatf("%m. *** rw.addr = %0d, rw.data = %0d, rw.kind = %s, rw.status = %s", rw.addr, rw.data, rw.kind.name, rw.status.name), UVM_HIGH); endfunction: bus2reg Thx, Assaf
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