Thanks for the feedback.
These advantages of SystemC are leading me to test the waters:
1. One can model a system at a higher level of abstraction, and then dive in and do hardware description.
2. Due to its object oriented nature, there might be fewer lines of code (relative to verilog).
3. Free simulation!, Faster simulation using GPUs...
But, you are telling me that for RTL design, I should not bother with SystemC?
PS: The systems I work on have both analog and digital content and involve DSP.