acrussp replied to wilson_on's topic in UVM SystemVerilog DiscussionsYes. I can't find it at the moment but some time with Google search should turn up a whole library a guy had written that uses Python as the verification language via the dpi. Seemed very interesting but I never did more than skim the docs.
Well, a bit late replyiing but... Mentor only says this as they want you to write everything so it could maybe run on Veloce. It's not realistic though. Simple example would be multiple sequences running in parallel generating traffic at different rates and making use of arbitration algorithm (possibly custom) in the sequencer. You can't push these delays off to the driver without seriously impacting how your system operates. In most situations I've seen you want late generation ( in other words, don't generate until you are read to send so you can take into account current state of system). If you go trying to push off your delays to the driver this could succeed with a single sequence but you quickly run into problems with multiple sequences running in parallel. You could still do the above and be Veloce compatible by using events but it's not really a natural way to code so....