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Everything posted by rsmitra09

  1. PSS allows both control-flow and data-flow dependencies. Control flow is among statements within an activity, whereas data-flow permits inferencing which additional actions to be scheduled and when. However, the semantics for mixing these 2 kinds of flow is not specified in the manual. For example, take the code given below, which has 3 actions defined in it: read3_write3: User explicitly calls read and write inside a loop, and inferencing is not needed. read1_write3: User explicitly calls read outside the loop, and calls write inside the loop, and again inferencing is not needed. read_write_implicit: Here, the semantics are not clear. The loop only calls write, which requires a data and hence read will be scheduled before it. Should the read be scheduled inside the loop or outside it? ie, is read_write_implicit equivalent to read3_write3 or read1_write3? An additional question related to this code is: the bind command is used to bind (input or output) ports of different actions. But in our code, the data (eg read3_write3::i) is read from one action and written to another action, so it is neither input nor output. Either an additional specifier 'inout' should be introduced, or the bind keyword should allow ports to bind to non-ports also. In the example, I have assumed the 2nd alternative. component IO { action READ { output int i; exec body C = """scanf("%d\n", &{{i}});"""; } action WRITE { input int i; exec body C = """printf("value %d\n", {{i}});"""; } } component pss_top { IO s; action read3_write3 { int count; int i; activity { bind s.READ.i i; bind i s.WRITE.i; count = 0; repeat while(count<=3) { s.READ; s.WRITE; count = count + 1; } } }; action read1_write3 { int count; int i; activity { bind s.READ.i i; bind i s.WRITE.i; count = 0; s.READ; repeat while(count<=3) { s.WRITE; count = count + 1; } } }; action read_write_implicit { int count; int i; activity { bind i s.WRITE.i; count = 0; repeat while(count<=3) { s.WRITE; count = count + 1; } } }; action top { activity { read_write_implicit; read1_write3; read3_write3; } }; }
  2. Clarification on example 57

    Agreed that (a;b)&(c;d) may possibly be illegal because a and d use the same resource. But if a takes very less time to execute and c takes a long time, then a and d may not overlap their execution times, and so the conflict may not actually arise during simulation. So, my question is: is the legality check done statically (and pessimistically) or dynamically (ie during simulation time)?
  3. grammar corrections

    I found one more bug in the grammar: For example-71, which has an action declaration inside an activity, the grammar has to be updated: activity_stmt: : ... | action_field_declaration // add this rule ... Another bug is mentioned in the post "one full example".
  4. Hi, Based on Accellera's recently released standard, I am now developing a PSS front-end. While doing this, I came across several grammar problems, and also some typos in the example code given in the document. In this email, I have attached 2 text documents: (1) error_grammar.txt : a list of grammar problems, and their suggested fixes. (2) error_examples.txt : a list of typo mistakes in the examples. The page numbers mentioned are the pdf page numbers, NOT the printed page numbers. I would like to hear from the others if these mentioned fixes are good, or other changes are required. Regards.. Raj S Mitra, rsm@verikwest.com error_examples.txt error_grammar.txt
  5. one full example

    Given that this concept of a high level test specification is fairly new, what is critically needed is one complete example which shows the entire flow of usage. The videos from DAC-2017 show some code snippets from an UART/DMAC example, but that also does not show the complete code. So I have taken the code snippets from the DAC tutorial, and put them together as one full code (see below). Can this example be corrected, more details added (for instance, variations for inferring from incomplete specifications) and the full code be added to the next version of the manual? While creating this example, I noticed one problem in the grammar. In the instantiation of action rd_i in pss_top, where will the action read_in_a be found? The grammar allows only one identifier as the type, so the following hierarchy of names is not allowed today: action data_rx_a { uart0.read_in_a rd_i; // "uart0." prefix added } The full code (as I have understood it) is given below: // uart example, copied from dac2017-part1 video // approximate time of occurance - mentioned as comments // some extra lines added, for missing symbols // at 30:31 ====================================== stream data_stream_s { rand int size; int addr; //added } buffer data_buff_b { rand int size; int addr; //added } // at: 42:50 ========================================== resource dma_channel_r { bit[5:0] instance_id; // added } struct dma_xfer_params_s { rand bit[1:0] mode; rand bit[31:0] src_addr; rand bit[31:0] dst_addr; rand bit[5:0] chan; } // at: 44:20 =================================== component uart_c { //import dma_xfer_pkg::*; // not needed, using above code resource uart_r {}; pool [1] uart_r uart_p; bind uart_p {*}; action read_in_a { output data_stream_s data; lock uart_r myuart; constraint c1 {data.size % 4 == 0;} }; } // at: 45:20 =================================== component dmac_c { pool dma_channel_r chan_p; bind chan_p {*}; action q2m_xfer_a { // details added from 42:50 input data_stream_s in; output data_buff_b out; lock dma_channel_r chan; rand dma_xfer_params_s params; //rand duplicated here? constraint c1 {in.size == out.size; } constraint params_c { params.mode == 'b01; params.src_addr == in.addr; params.dst_addr == out.addr; params.chan == chan.instance_id; } } } // at: 47:06 =================================== component pss_top { uart_c uart0; dmac_c dma0; pool data_stream_s stream_p; bind stream_p {*}; pool data_buff_b buff_p; bind buff_p {*}; action data_rx_a { // at 32:29 =============== read_in_a rd_i; // need to add "uart0." prefix q2m_xfer_a q2m; // need to add "uart0." prefix constraint c1 {q2m.in.size % 4 == 0;} bind rd_i.data q2m.in; activity { parallel { rd_i; q2m; } } } }