amal.khailtash

I can see there is a tlm::tlm_transport_channel, but no corresponding uvm::tlm_transport_channel/uvm::tlm_transport_port/uvm::tlm_transport_export/uvm::tlm_transport_imp. I am looking for an example of such port/channel use. It seems uvm_tlm_transport_channel is missing from UVM SystemC implementation as well as specified in the RELEASENOTES. But there is no mention of their SV counter parts uvm_*_transport_* uvm_blocking_transport_(port|export|imp) nonblocking_transport_(port|export|imp) transport_(port|export|imp)

I am working on a TLM model of a design where the design has initiator and target (custom) interfaces. Some interfaces are unidirectional, just data going from initiator to target, but some are bi-directional. Think of a memory interface, where a design makes requests (reads/writes) and gets the response back. In this example, request could be address/and write data and response could be a completion status and a read data if the operation is read. I was looking at the transport port/export in SV where the initiator sends an atomic request and gets a response back.

I am looking for a bidirectional port/export in UVM SystemC implementation. I could find uvm_*_transport_port/uvm_*_transport_export as well as uvm_*_master_port/uvm_*_master_export/uvm_*_slave_port/uvm_*_slave_export in UVM SystemVerilog implementaion. Is there any bidirectional implementation in SystemC that might be called something else or should I implement the counter parts of the above, in SystemC? I can always use multiple single directional port/export, but it would be easier to have one port for ease of connection/implementation. -- Amal

Sorry, but this question is related to SystemRDL, but there is no discussion board for that, so I post here that is the closest. IP-XACT addressBlock has a range attribute that I can define and leave some space at the end of the addressBlock. I would like to do something similar in SystemRDL. I tried defining a regfile (no associated a top-level RTL), but I cannot see an equivalent range attribute. Then I thought about using an addrmap (although it has an associated RTL view), but again that one does not have a range attribute either! How do I leave some reserved space at the end of an addrmap or a regfile? If I had an element after the last register, I could leave some space. But not sure what to do at the end? Note that this regfile is meant to be instantiated in various other addrmaps and need to have a specific range. Is there such a thing as a null register? Maybe I should declare a register array with no access "sw = na" attribute?

Is the grammar for P1735 publicly available or do you need to be a contributing member? -- Amal

Great! Thanks,

What happened to the TGI.WSDL in 2014? There 2009 WSDL version is here: http://www.accellera.org/XMLSchema/SPIRIT/1685-2009/TGI/TGI.wsdl Is there plan for Accellera to provide this WSDL in the future? -- Amal