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maehne

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Everything posted by maehne

  1. As my quotes from the LRM show: It is not forbidden, but strongly discouraged. Therefore, a SystemC implementation may issue a warning if the module hierarchical is not respected, but it is not required to do so. The proof-of-concept implementation of SystemC currently doesn't do this.
  2. define sc_main in VS 2017

    It is correct that your SystemC application compiles and runs correct if you leave the default entry point at main() and provide yourself only sc_main(). This is by design, as you can read up in clauses 4.2 and 4.3 of IEEE Std 1666-2011. Subclause 4.3.2 states: The SystemC library provides a main() function, which calls sc_elab_and_sim(), and which in turn then calls the sc_main(), which you have to provide to set up your model and control elaboration and simulation.
  3. Yes, in SystemC AMS, as in other analog/mixed-signal simulators, good precision usually requires the setting of a small enough simulation time step. As a rule of thumb, you should set the time step in a cluster of connected TDF/ELN/LSF modules such that the signal with the highest occurring spectral frequencies is sampled with at least 5 to 10 samples per period of the highest frequency for moderate accuracy and about 20 samples per period for good accuracy. Does your configured module time step respect this with respect to the cut-off frequency and selected input signal? For best simulation performance, you module srcs and sample should be connected via TDF ports and TDF signals and not via TDF<->DE converter ports and DE signals. Then, you can profit from the fact that the srcs and sample module will end up in the same static TDF schedule, which is executed by the SystemC AMS simulation kernel. I would also recommend that you don't include the SystemC/SystemC-AMS headers using <systemc.h> and <systemc-ams.h> as this pollutes the public namespace. Instead, prefer the recommended headers <systemc> and <systemc-ams>.
  4. User Guide for systemc 2.3.2

    I totally agree that it would be great if the example code from the "SystemC: from the ground up" book would be made available again on the internet. It is best to ask @David Black for that as he is one of the authors of the book. By the way, the second edition of the book has its own homepage: http://scftgu.com/ Unfortunately, it doesn't provide an archive with the example code sources either.
  5. I suggest that you read in IEEE Std 1666-2011 the introduction to the socket concept in clause 10.4 and then the rules for: multi-sockets in clause 16.1.4.4 tlm_base_initiator_socket and tlm_base_target_socket in clause 13.2.4 of. ports in clause 5.12.4 exports in clause 5.13.4 Initiator sockets are derived from a port for interface method calls on the forward path and has an export for interface method calls on the backward path. For target sockets it is vice versa. Therefore, when you bind() sockets, the bind actually happens on the port and export. That's why the constraints on usage for ports and exports apply. For sc_port the following paragraph is relevant: For sc_export it is: Therefore, your example may not generate an error during compilation and elaboration, but may still disrespect the normal discipline of the module hierarchy.
  6. How to compare VCD files

    I guess you tried comparing traces in "impulse". In that case, you need to make sure that you have obtained the correct license. You need to unlock the "analyze" variant of impulse.
  7. C-API for SC-AMS

    Your arguments for foreign model reuse are valid and this is recognised by the people behind the modeling language definitions and simulators. That's why basically all common simulation tools provide some API to control the simulation programmatically from a foreign process including some means for data exchange (for stimuli and monitoring). Also, these tools usually provide a way to import foreign functions (usually at least those following the C calling conventions). By these ways, you can implement the synchronisation and data exchange mechanism between your models according to your needs. SystemC (AMS) only differs that the models are already written in C++, which provides even less friction to interact with the C APIs of other simulators. However, you have to keep in mind the simulation semantics of these models, which are imposed by the embedded simulation kernel during simulation. You have to make sure that you don't interfere with them through your API use in a way that disturbs the model execution. To that end, you should read up on the elaboration and simulation semantics of SystemC (AMS) in the respective LRMs. You will see there that both language standards define dedicated callbacks, which allow you to take action during all phases of elaboration and simulation, which facilitate the coupling of SystemC models with other simulators/modeling languages. You either have to implement the interface yourself or use the EDA tool vendor-specific solutions, which have been available for years, e.g., QuestaSim is capable to mixed SystemC/VHDL/SystemVerilog models. Another example is the SystemC AMS IDE COSIDE, which provides tool couplings to all major HDL simulators as well as to MATLAB/Simulink, dSPACE, and ngspice. For simple cases like you describe with your C application, which shall provide stimuli to your TDF model, you often get away with doing model synchronisation/data exchange via blocking read/write calls from within your SC_METHODs, SC_THREADs, or TDF processing() callbacks on some communication channel to your foreign model executed by another simulator. In the simplest case, this could be your stdin/stdout streams. Other popular options would be named pipes, sockets, or some some RPC API. The choice will largely depend on the modeling language/simulation tool, which you have on the other side. If they provide the possibility to import foreign C functions, they usually support all mentioned options. I think you might find interesting the technology demonstrator, which was presented by David C. Black at DVCon 2013 as part of the "Increasing Productivity with SystemC in Complex System Design and Verification" tutorial and made available on GitHub a while back: https://github.com/dcblack/technology_demonstrator You might also find other videos interesting, which are available from the Accellera website: http://videos.accellera.org/videos.html
  8. When exactly events are created?

    The output exposes a misconception you have about the semantics of sc_start(). Once you call sc_start(), you completely hand over control to the DE simulation kernel of SystemC to process all events, which are created by the SC_METHODs and SC_THREADs. Execution of sc_main() only continues *after* sc_start() returns because there are no events to process anymore. Because you don't call dont_initialize() after registering your SC_METHODs, they get executed right after start of simulation at 0 ns. Your request method then notifies the event with a 20 ns delay, which triggers your reply method at 20 ns. You notify from sc_main has no effect as you don't hand over control to the simulation kernel. Your message "MWE created" gets executed after the simulation finished. To generate stimuli for your model, it is common practice to create a custom module with SC_THREAD(s) that generate the stimuli. You may also do some monitoring from this thread. Conceptually cleaner is to separate stimuli generation and monitoring into separate modules. From your modeling goals, it seems that you could benefit from using Transaction Level Modeling (TLM), which is part of the IEEE Std 1666-2011. However, I suggest that you get first a bit more familiar with the basic concepts of SystemC and TLM by reading a good introductory book on SystemC(/TLM), e.g., SystemC from the ground up. There also some good introductory presentations, which you can find in the archives of the different SystemC User Groups.
  9. Using Debug mode.

    If you use the Makefile provided along the simple_fifo example, it should get compiled with debug symbols. On the console, you should see that the .cpp files get compiled with the "-g" switch. To actually make use of the debugging symbols, you have to execute the example in a debugger such as gdb (as Roman already pointed out). By the way, "make -d" does not influence which flags are passed to the C++ compiler. It just makes the output of make itself more verbose.
  10. C-API for SC-AMS

    Well, SystemC and SystemC AMS are just C++ libraries, which define the functions and classes that form a domain-specific language suitable for modeling complex digital and mixed-signal systems at a high level of abstraction based on different models of computation (e.g. Discrete Event, Timed Data Flow, Electrical Linear Networks, Linear Signal Flow) as well as their simulation using the embedded simulation kernel. As they are C++ libraries, it is straightforward to wrap any SystemC (AMS) model into a custom C function (or set of C functions), which respects the specific API that you need to integrate it into your top-level model. You just have to limit yourself to the basic C datatypes in the function interface and to declare the functions as extern "C". From these C functions, you will have to set up the model and control its execution by providing stimuli and feeding the SystemC models reactions back to your external model. You may also implement a custom primitive channel as a co-simulation bridge to another model running in a different simulator. To facilitate synchronisation in such scenarios, IEEE Std 1666-2011 provides async_request_update() (see clause 5.15.6). That said, the main purpose of SystemC (AMS) is create virtual prototypes of entire complex SoCs early on in their design process to enable, e.g., architecture exploration, Hw/Sw partitioning, and early firmware development. This virtual prototype serves as a kind of golden reference during refinement. Therefore, your SystemC virtual prototype usually "sits on top", i.e., refined component models executed in external simulators are usually embedded via a module wrapper, which provides the SystemC interface for communication and makes use of the C API of the external simulator to communicate with the foreign model. Given that, I don't see much need for any additional dedicated C API. What are you missing?
  11. I am happy I could help and that you can now use the SystemC and SystemC AMS libraries on Visual Studio!
  12. Even though the INSTALL instructions for the SystemC AMS PoC mentions only Visual C++ 8.0/9.0 as well as SystemC 2.2, I would recommend you that you to try to build against the most recent release of SystemC 2.3.2 using either Visual Studio 2015 or 2013. Recent Visual Studio versions should still be able to open and convert the old provided solution files. Compared to SystemC 2.3.0, SystemC 2.3.2 fixed many errors, among them an issue with the sc_event_or_list type mentioned in your error log. Recent Visual Studio version are much more conformant to the ISO/IEC C++ standard. As I am using mostly the GNU and Clang toolchains on non-Windows platforms, I cannot help you further at the moment.
  13. Install SystemC on Visual Studio 2017

    Do you provide a proper definition of "void sc_main(int argc, char* argv[])" in your application as entry point for your simulation? Have you made sure to not have a function main() defined at the same time? In the latter case you would need to call explicitly sc_elab_and_sim(argc, argv) to hand over control to SystemC for elaboration and simulation (which will include a call to sc_main()). Confer to IEEE Std 1666-2011 clause 4.3 for details.
  14. User Guide for systemc 2.3.2

    Maybe you could share what was the cause and how you fixed the issue?
  15. TOP MODULE LOOPING

    You don't seem to be familiar enough with the concept of discrete event driven simulation. Simulation stops once all events have been processed by the processes of your system or the simulation end time has been reached. If you want your simulation to continue, you have to modify your stimuli process(es) so that they keep generating stimuli as long as you wish. Again, I recommend you to read a good introductory book on SystemC before continuing with your modelling efforts!
  16. How to initialize sc_fifo

    @David Black hinted you to the right solution: Look up in a good book on C++ how to properly initialise member variables in a constructor! For resources, check out this site. As an additional hint: instead of initialising your local member variables sc_fifo_e::a and sc_fifo_array::q, you are declaring local variables in their respective constructors with the same name as your member variables. These shadow the member variables and are destroyed once execution leaves the constructor: class sc_fifo_e { sc_fifo_e() : a(10) // member variables need to be initialised in order of declaration // in the constructor's initializer list { // sc_fifo<int>a(10); // declares a local variable } public: sc_fifo<int>a; };
  17. Does system C support matrix of unknown size

    David is right about the wrong declaration of your matrix. However, your code has several issues related purely to C++ and not SystemC: Your local variables m, n in constructor sc_fifo_array shadow the member variables m, n. Decide at which scope you need your matrix and drop the other pair. I would recommend to declare m and n as constants and assign their values upon declaration or in the constructor's member variables initialization list. I would recommend to not use raw memory allocation for your matrix. It will be a hassle to ensure that it gets correctly deallocated. Instead consider to use an appropriate container providing you the functionality of a matrix. You may consider, e.g., the Eigen library. Advantage is that these containers usually implement efficiently additional convenient operations, which you otherwise have to implement and test yourself.
  18. TOP MODULE LOOPING

    Your description and code snippet does not provide enough context for an external person to understand your intent. Please, provide more context and possibly a sketch of you system architecture so that the code snippet can be correctly interpreted. What do you mean by "to change the values of my ports"? If each layer differs from the previous, what is a point to use a loop instead of a simple to understand sequence of statements? Do you really need to expose the reader to so much details (i.e. 26 layers) to describe your problem? Try to reduce your example and enhance it with enough context so that we get a better idea of what you want to achieve. You seem to be not yet enough familiar with the fundamental concepts of SystemC. Consider to read a good introductory book to SystemC!
  19. User Guide for systemc 2.3.2

    Your example code uses many features, which have been deprecated for good reasons already in IEEE Std 1666-2005. The Accellera proof-of-concept implementation SystemC 2.3.2 of IEEE Std 1666-2011 continued the effort to improve the code quality and facilitate the maintenance of the implementation by removing long-deprecated features and improve the compatibility with modern C++ compilers and coding techniques. I recommend that you familiarise yourself with the "Modern C++" concepts introduced by C++'11, '14, and '17 and start to modernise your SystemC models. Following are some hints to get you started: Use the <systemc> header instead of <systemc.h> and explicitly use the appropriate namespace prefixes or using statements Use std::string instead of the long deprecated sc_string When calling sc_core::sc_start(), always pass the appropriate time unit as second argument or pass a sc_core::sc_time constant/variable Make sure to compile your model with the same flags that were used during the compilation of the SystemC library itself. Especially make sure that everything is compiled against the same language standard! Otherwise, you will face link problems! Besides a good book on C++, I also recommend you to read a good introduction to SystemC, e.g., "SystemC from the Ground Up".
  20. Then, you have to express the vectors as an appropriate data type, which fulfils the conditions for the template parameter T of the port/bound signal (cf. to clause 6.4.3 of IEEE Std 1666-2011), i.e., the data type needs to implement the equality operator==, stream operator<<, and assignment operator= as well as a default constructor. E.g., you could try to use a suitable data type from the Eigen library.
  21. How to compare VCD files

    This kind of functionality needs to be implemented by your VCD trace file viewer. E.g., the impulse plug-in for Eclipse available from toem.de seems to offer this kind of functionality in its "analyze" variant.
  22. The compilation command is correct except for the SystemC AMS version. You also have to check that you have chosen the appropriate lib directory for your target platform (e.g., "linux" signifies a 32-bit i686 Linux platform, "linux64" a 64-bit x86_64 Linux platform). You can try to adapt the following Makefile snippet as a starting point: # Compiler and linker flags SYSTEMC_ARCHITECTURE?=linux SYSTEMC_INCLUDE_DIRS?=-I/<directory_path_to_SystemC_2.3.0>/include –I<directory_path_to_SystemC_AMS 2.1>/include SYSTEMC_LIBRARY_DIRS?=–L/<directory_path_to_SystemC_2.3.0>/lib-${SYSTEMC_ARCHITECTURE} -L/<directory_path_to_SystemC_AMS 2.1>/lib-${SYSTEMC_ARCHITECTURE} CXXFLAGS=-g -Wall -I. $(SYSTEMC_INCLUDE_DIRS) LDFLAGS=$(SYSTEMC_LIBRARY_DIRS) # List of all ecutables to be compiled EXECUTABLES = sim01_tb sim02_tb # .PHONY targets don't generate files .PHONY: all clean # Default targets all: $(EXECUTABLES) # Rules defining the targets and their dependencies and how to generate # the first from the latter. # 1st example can be directly compiled, as it only depends on one # CPP file and the headers of th source and the sink, which also # include their implementation. sim01_tb: sim01_tb.cpp source.h sink.h $(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $< -lsystemc-ams -lsystemc | c++filt # 2nd example is constituted of two CPP implementation files, which have # to be first compiled to object files before being linked. For # big models, this is preferable, as the object files can be selectively # updated after individual modifications. sim02_tb: sim02_tb.o my_module.o $(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ -lsystemc-ams -lsystemc | c++filt # GNU make knows how to compile a CPP file using compiler $(CXX) and # the flags $(CXXFLAGS). sim02_tb.o: sim02_tb.cpp source.h my_module.h sink.h my_module.o: my_module.cpp my_module.h # Clean rule to delete temporary and generated files clean: rm -rf *~ *.o *.dat *.vcd *.dSYM $(EXECUTABLES) It compiles two test benches sim01_tb and sim02_tb.
  23. impulse is a good trace file viewer for visualising the results of simulation runs of SystemC models. "scv" hints that this format is not part of the TLM standard, but part of the SystemC Verification (SCV) library, which you can also download from the Accellera website: http://accellera.org/downloads/standards/systemc The SCV tar ball contains in the docs/ directory several PDF documents, which outline the use of transaction recording. As you can guess from their publication dates in 2003, this mechanism predates TLM-2.0. As I never used that API myself, I cannot provide further insight/guidance.
  24. If you insist to instantiate 16 separate ports to transfer each array element separately from each other, you will also have to write/read the elements in your code one after another using, e.g., a loop over the array. From a simulation point of view, all writes will happen at the same time.
  25. SystemC and latency simulation

    You might find the following thread helpful to address your needs:
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