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sathyakiran.p

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About sathyakiran.p

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  • Birthday October 10

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    Male
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    Hyderabad
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    UVM concepts
  1. sathyakiran.p

    referring/connecting env in a test

    solved the issue by connecting my sequencer with actual sequencer in test.
  2. Hi, Following is the sample code class a_env extends uvm_env .... endclass class basic_test extends uvm_test a_env a_env1; a_env1 = a_env::type_id:create("a_env", this); endclass class b_env extends uvm_env a_env a_env2; // only reference ... endclass class my_test extends basic_test b_env b_env1; virtual function void connect_phase( umv_phase phase) super.connect_phase(phase); b_env1.a_env2 = a_env1; endfunction .. endclass I am getting NULL_OBJCT access error with the above code.. can anyone helpout? Thanks, Satya
  3. sathyakiran.p

    uvm_test call inside c++

    our DV environment is in such a way that I need a C++ file to add tests. There is no other interactions b/w c++ and uvm,except, just calling the uvm test. I can run the uvm tests using perl/shell scripts, but, want to support it with our current environment. Let me know, if there is any way. Thanks, Satya
  4. Hi, I have testbench in uvm environment. I want to call uvm_test from a c++ file. That will be my testcase. example: class basic_test extends from uvm_test; ..... endclass I want to call basic_test inside a c++ file. Let me know, if you need any further information. Thanks, Satya
  5. Hi, we see different kind of failures when we run simulations, like assertion error, uvm_error. How do we report outside UVM errors in report phase to give the TEST STATUS? I am getting some psl/ovl/sva assertion errors, but, UVM part is not reporting any error. how do I report test STATUS?? Thanks, Satya
  6. Thanks David for clarification.
  7. I got the correct solution for it uvm_do_with From: `uvm_do_with(item,{ item.addr = addr; item.data = data; }); To: `uvm_do_with(item,{ item.addr = addr1; item.data = data1; }); The above one will work... I don't know the reason behind this... Thanks, Satya
  8. I have written the code just for sample.... actual syntax is like you have mentioned.... fields are also correct.. those are just typos... It is something problem with uvm_do_with. Thanks, Satya
  9. Following is the sequence code class basic_sequence extends from uvm_sequence(#sequence_item); sequence_item item; task body() fp1 =fscanf("abc.txt", addr, data); `uvm_do_with(item,{ item.addr = addr; item.data = data; }); endtask endclass I have constrained addr and data from file reading data. It is not happening with the above code. data_item is getting a random value. I have written a user-defined task to solve this problem like below task do_rw(int addr, int data); begin item = sequence_item::type_id::create("item",,get_full_name()); item.wr_adr.rand_mode(0); item.wr_dat.rand_mode(0); item.wr_adr = addr; item.wr_dat = data; start_item(item); randomize(if_item); finish_item(item); end endtask inplace of uvm_do_with call uder defined do_rw task like below fp1 = fscanf("abc.txt", addr, data); while(!eof(fp1) { do_rw(addr, data); } This will work. I used above solution to work. I really don't understand why uvm is not supporting it with uvm_do_with. any answers for fit?? Thanks, Satya
  10. Thanks alot david. It is working fine.. one small correction `declare_p_sequencer(SEQR_TYPE) => `uvm_declare_p_sequencer(SEQR_TYPE), SEQR_TYPE is sequencer name. Regards, Satya
  11. Hi David, when we define run_phase and other phases(main_phase, reset_phase...) in a component. It will override all other phase, but, execute only run_phase?? Please correct me I am wrong. Thanks, Satya
  12. sequence will start execution in main_phase , where as, driver will start execution in run_phase. Both are concurrent phases. Thanks, Satya
  13. Following is the example class my_sequence extends uvm_sequence... string file_name; `uvm_object_utils_begin(mysequence) `uvm_field_string(file_name,UVM_DEFAULT) `uvm_object_utils_end endclass class basic_test extends from uvm_test function build_phase(..) set_config_string("*", "file_name", abc.txt); endfunction endclass.. I am passing file_name(abc.txt) from test with set_config_string, but, it is not taking effect. I did the same thing in driver. it worked well. does UVM supports, overriding local variables in sequence. Please let me know... Thanks, Satya
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