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  1. NEW - The Coverage Cookbook - A methodology focused on effective coverage adoption In functional verification, methodology is the bridge between tools and technologies, which creates a productive, predictable, and repeatable solution. This first phase of the Coverage Cookbook introduces a methodology focused on coverage that complements the Universal Verification Methodology (UVM), the industry standard verification methodology that has gained a significant following over the last several years. The Coverage Cookbook is a series of online linked articles designed to help you master the methodology and process required to effectively adopt a coverage-driven verification flow by providing: * a foundation of understanding on the various types of coverage metrics available today, and how to effectively use them * a repeatable process for creating functional coverage models distilled from a specification * real-world examples used to demonstrate the functional coverage modeling process More information on the Coverage Cookbook can be found at http://go.mentor.com/coverage-cookbook-news
  2. http://www.mentor.com/company/news/mentor-extends-uvm-connect-support-ovm Mentor Graphics Extends UVM Connect to Support OVM WILSONVILLE, Ore., September 10, 2012 — Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of an update to the popular Universal Verification Methodology Connect (UVM Connect) to bring the benefits of it to the Open Verification Methodology (OVM) community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well. Market research shows OVM continues to be a popular and growing methodology for verification teams. About half of all teams have adopted OVM as their verification base-class library and it continues to lead among all other alternatives. To support the OVM community, the Mentor Graphics® Verification Academy offers a vibrant user community forum and contributions area that encourages users to share their OVM experiences and enhancements with each other. The Verification Academy also has educational and training information to help the novice to the expert. “When looking at functional verification trends, it was clear that OVM remains important to the verification community and its growth is projected to continue,†said Harry Foster, chief verification scientist of the Design Verification Technology division at Mentor. “Mentor continues to demonstrate its support of OVM by making significant new UVM capabilities available to the OVM community and promoting a vibrant OVM community at the Verification Academy.†The enhanced UVM Connect provides standard TLM connectivity between models written in SystemC and OVM SystemVerilog to maximize IP reuse. It is designed to work with all simulators that support the IEEE 1800 SystemVerilog and IEEE 1666 SystemC standards and can accommodate different inter-language instantiation schemes used in various solutions. Feedback from verification teams with simulators from multiple suppliers was taken into account to provide broad industry support. “The full benefits of UVM Connect are now available to verification teams using OVM to allow them to connect and control OVM from other environments such as SystemC,†said Tom Fitzpatrick, verification methodologist of the Design Verification Technology division at Mentor. “The enhanced UVM Connect solution is built to preserve the easy migration from OVM to UVM and shows our continued commitment to bring UVM features back to the OVM community.†About UVM Connect As design teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models becomes imperative. Design and verification teams work with a number of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language. By facilitating cross-language communication via standard transaction level modeling (TLM) interfaces, UVM Connect allows for the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. With the latest enhancement, both UVM and OVM verification teams can maximize their productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM and OVM state and control flow from outside SystemVerilog. Availability The extensions are available in the updated UVM Connect 2.2 kit. It is available immediately and can be downloaded from the Mentor Verification Academy website: http://verificationacademy.com/ or the Accellera Systems Initiative UVM contributions area at http://www.uvmworld.org/contributions.php. Verification Academy modules on basic and advanced OVM and UVM use, as well as additional training material and online documentation, are also available on the Verification Academy website.
  3. September 13, 2012 Online Mentor Graphics Seminar 9:00 AM - 10:00 AM US/Pacific Convert to Local Time Register Overview Many hardware blocks are designed to interact with software using memory mapped registers. In the final implementation, the system level software, running on a CPU, reads and writes these registers via a bus interface on the hardware block. With UVM sequence based stimulus, accesses to these registers are made via a bus agent, sometimes in a directed way that emulates software accesses, sometimes using constrained random stimulus. This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents. The API enables c code to be compiled and then run on the host workstation during the simulation of a UVM environment. What You Will Learn Review of a register-level testbench architecture Tradeoffs associated with C stimulus alternatives How to extend your environment to accept C stimulus How to use the c_stimulus_pkg to use C code as stimulus in your environment
  4. Event: Graph Based Verification - DVClub Date: 2 July 2012 Time: 11.30 to 14.00 (GMT) The next DVClub takes place on Monday, 2nd July and will focus on Graph-Based Verification! Why not register to hear three speakers bringing their own unique perspective: Staffan Berg, Mentor Graphics Graph-Based Verification in a UVM Environment Adnan Hamid, Breker Verification Systems The Graphic Truth about SoC Verification: Stitch and Ship Doesn't Work Olivier Haller, STMicroelectronics Real-world usage of Graph Based Verification to verify complex SoC designs Registration and additional details of the presentations and speakers can be found here. DVClub is organized by TVS who are committed to making DVClub accessible to everyone and you can join the meeting remotely via the Internet or physically in several locations: Bristol: Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP Cambridge: ARM, 110 Fulbourn Road, Cambridge, CB1 9NJ Eindhoven: Venue details to follow Edinburgh: Not Confirmed, details to follow Grenoble: STMicroelectronics - Polygone Scientifique, 12 Rue Jules Horowitz, Grenoble Remote Access If you attend remotely why not do what many other companies do - book a room and invite your colleagues along so you can discuss and debate the topic.
  5. UVM Connect Web Seminar See go.mentor.com/uvm-cnx for more information on Mentor's UVM Connect web seminar and to register. Date: 10 April 2012 Time: 8:00 AM - 9:00 AM US/Pacific (Convert to Local Time) Overview UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment. It also includes SystemVerilog designers who want to use SystemC models as reference models in their environment or any other application that requires components of both languages to run together. What You Will Learn Review the principles of the TLM1 and TLM2 standards, including the basic port/export/interface connections in both SystemC and SystemVerilog How to establish TLM-based connections between SystemC and SystemVerilog UVM components How to write converters to transfer transaction data across the language boundary How to wrap a SystemC reference model for use as a SystemVerilog UVM verification component How to access and control key aspects of UVM simulation from SystemC
  6. See go.mentor.com/uvm-exp for more information on Mentor's UVM Express web seminar and to register. Date: 29 March 2012 Time: 8:00 AM - 9:00 AM US/Pacific (Convert to Local Time) Overview UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation. The UVM itself is a powerful class library and associated usage guidelines for creating reusable transaction-level verification environments and components. Unfortunately for many teams, UVM’s reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future. What You Will Learn How to raise the abstraction level of your test by structuring your environment to use Bus Functional Models (BFMs) using tasks in interfaces to facilitate test writing How to add functional coverage to an existing BFM-based testbench to measure the quality of your existing tests How to add constrained-random stimulus generation to an existing BFM-based testbench to improve the productivity of the test write and improve the overall quality of your test environment. How to instantiate and configure VIP components to simplify the adoption of functional coverage and constrained-random stimulus How to move from initial adoption with UVM Express to a full UVM-based environment
  7. http://www.businesswire.com/news/home/20120222005387/en/Mentor-Graphics-Drives-Broader-Adoption-UVM Mentor Graphics Drives Broader Adoption of UVM WILSONVILLE, Ore., Feb. 22, 2012—Mentor Graphics Corporation (NASDAQ: MENT) today announced expanded support for the Universal Verification Methodology (UVM). The UVM delivers productivity gains made possible by reuse in functional verification. For verification teams with minimal exposure to UVM, the first step to implement a UVM-based verification environment is simply getting started. To facilitate that first step, Mentor introduces UVM Express, a way to progressively adopt a UVM methodology. Other verification teams have an established UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved. For those verification teams, Mentor introduces UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog. “Mentor continues to see massive interest in UVM, and we are committed to leading the effort to make UVM an integral part of every functional verification flow,†said John Lenyo, vice president and general manager of the Design Verification Technology division at Mentor Graphics. “For verification teams using UVM for the first time, UVM Express makes getting started easy and intuitive, and extends rapid productivity gains to a broader scope of design projects. With UVM Connect, we’ve created a link between abstraction levels that enables design and verification engineers to take advantage of each level’s best features without sacrificing the ability to reuse work.†  About UVM Express Verification teams often have time and budget constraints that make adoption of new methodologies difficult. These teams are exactly the kind of teams that the UVM is meant to help, but the first step towards adoption is currently too high. UVM Express provides a way to build the testbench environment, a way to raise the abstraction level, a way to check the quality of tests and a way to think about writing tests. Each of the steps outlined for UVM Express is a reusable piece of verification infrastructure. These UVM Express steps are a way to progressively adopt a UVM methodology, while getting verification productivity and verification results at each step. Using UVM Express is not a replacement for full UVM, but instead enables full UVM migration or co-existence at any time. UVM Express helps everyone, regardless of their experience level, to accelerate time to success. About UVM Connect As design teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models becomes imperative. Design and verification teams work with a plethora of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language. By facilitating cross-language communication via standard transaction level modeling (TLM) interfaces, UVM Connect allows for the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. It lets verification teams maximize productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM state and control flow from outside SystemVerilog. Availability UVM Express and UVM Connect functionality is available immediately and can be downloaded from the Mentor Verification Academy website: http://verificationacademy.com/. Verification Academy modules on using UVM - UVM Express and UVM Advanced – as well as additional training material and online documentation are also available on the Verification Academy website. About Mentor Graphics Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/. Mentor Graphics and Mentor are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
  8. The Design TechForum contains some sessions that might be of interest to the UVM users at the upcoming event in Israel. Details on all the planned events can be found here. For the e user planning a move from using eRM to UVM, a session at the Design TechForum will cover this. Session Title: Migrating from eRM to OVM/UVM Location: Caesarea, Israel Date: 11 April 2011 Time: 13:15 - 14:00 Register: Click Here Session Abstract: This session looks at some of the challenges of moving from e/eRM to SV/UVM. It starts with a short UVM introduction, followed by some pros and cons of going down the UVM migration path. The session uncovers some of the well known pain points that e/eRM users encounter as they begin the process of moving to SV/UVM. Examples include: - Testbench/testcase separation - Extending classes - Configuring the testbench - Randomizing transactions - Checking - Signal mapping Sponsors: This event is not an Accellera event. Companies that sponsor this event can be found here.
  9. Uvm tlm port export import

    Keyur, If you are new to UVM, you might want to visit Verification Academy as you will find UVM/OVM information modules from basic to advanced. In the Advanced module set, Tom Fitzpatrick, verification technologist at Mentor Graphics, has a module titled "Understanding TLM" that will help you to answer the "when, where and why" of TLM. That module can be found at http://verificationacademy.com/course-modules/dynamic-verification/advanced-ovm-uvm-universal-verification-methodology/understanding-transaction-level-modeling. Fee-free access to these modules is allowed after registering to be a Verification Academy member (restrictions may apply). -Dennis
  10. http://go.mentor.com/mn5h WILSONVILLE, Ore., February, 21, 2011 - Mentor Graphics Corporation (NASDAQ: MENT) today announced comprehensive support for Accellera’s Universal Verification Methodology (UVM) across a broad range of products. Key technologies that support UVM include the Questa® advanced functional verification platform, the Questa MVC Verification IP library, the Veloce® emulation platform and the Certe™ Testbench Studio tool. UVM represents the culmination of Mentor Graphics’ effort to drive the development of an open verification environment that would promote better tool interoperability and verification data portability that began with the release of the first open-source Advanced Verification Methodology (AVM). AVM became the foundation for initial industry collaboration and fostered the development of the Open Verification Methodology (OVM) upon which the UVM is based. “Mentor recognized early that only an open source verification methodology would provide users the ability to write fully portable and reusable verification components,†said John Lenyo, general manager, Design Verification Technology division at Mentor Graphics. “We are proud to see that the technology we first developed in AVM and refined in OVM now continues as the core of UVM.†The Questa advanced functional verification platform offers native support for UVM by virtue of its industry-leading support of the IEEE Std 1800™ SystemVerilog standard on which UVM is based. This support includes comprehensive language feature support, native single-kernel simulation and full functional debug of SystemVerilog and UVM. The Questa Verification IP library has added native support for UVM. This allows users of UVM access to a comprehensive verification IP (VIP) solution that supports a wide range of industry-standard protocols without the need for any manual conversion, interoperability, or wrapper layers. The Questa Verification IP library dramatically improves verification coverage and helps speed the functional verification of integrated circuits (ICs) using industry-standard protocols. As a result, users of the Questa Verification IP library components can expect to see an improved time to market and a higher quality product. The Veloce emulation platform fully supports the UVM. The primary advantage to companies using both the UVM/OVM and the Veloce platform is the ability to use a single transaction-based testbench for both simulation and emulation—two technologies that are critical to the functional verification of large, complex system-on-chip (SoC) designs. The Certe Testbench Studio tool helps verification engineers harness the power of UVM by guiding the development of testbenches and registers that are correct-by-construction. The Certe Testbench Studio tool also delivers deep insight into the testbench construction and functionality via UVM testbench visualization, multiple class relationship views, full testbench object browsers, and register management. The Certe Testbench Studio tool enables rapid creation, complete understanding, and documentation of UVM testbenches for the most complex designs. UVM Based on OVM UVM 1.0 gains its leverage being based on OVM 2.1.1. OVM users will discover that great attention has been paid to backward compatibility to make it easier to migrate to UVM when ready. Conversion scripts take OVM 2.1.1-based code and convert it to UVM making it easy for current OVM users to adopt UVM at their own pace. Availability UVM is available from Accellera at www.accellera.org. OVM users can download the UVM kit from www.uvmovmworld.org where additional help and information specific to current OVM users can help them accelerate the adoption of UVM. About Mentor Graphics Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/. (Mentor Graphics, Questa, and Veloce are registered trademarks, and Certe is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.) For more information, please contact: Carole Dunn Mentor Graphics 503.685.4716 carole_dunn@mentor.com Ry Schwark Mentor Graphics 503.685.1660 ry_schwark@mentor.com
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