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Philipp A Hartmann

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Philipp A Hartmann last won the day on February 28

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About Philipp A Hartmann

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    Duisburg, DE

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  1. User Guide for systemc 2.3.2

    Annex C in the SystemC standard lists some deprecated features. In the SystemC proof-of-concept implementation, you find detailed information about changes in the RELEASENOTES file, but mostly only relative to the previous version.
  2. reset during wait(int)

    I agree with your conclusion that the observed behavior of the proof-of-concept implementation does not match the requirements of IEEE 1666-2011. I checked the code and it can be fixed by adding the check for resets to sc_thread_process.h (in the trigger_static() function): diff --git a/src/sysc/kernel/sc_thread_process.h b/src/sysc/kernel/sc_thread_process.h --- a/src/sysc/kernel/sc_thread_process.h +++ b/src/sysc/kernel/sc_thread_process.h @@ -485,5 +486,5 @@ sc_thread_process::trigger_static() #endif // SC_ENABLE_IMMEDIATE_SELF_NOTIFICATIONS - if ( m_wait_cycle_n > 0 ) + if ( m_wait_cycle_n > 0 && THROW_NONE == m_throw_status ) { --m_wait_cycle_n; I'll take this change to the language working group to get it fixed in a future version of the SystemC PoC kernel. Thanks for reporting! Greetings from Duisburg, Philipp
  3. SystemC CCI Build Issues

    Hi Ameya, thanks for the feedback! Can you please provide the following details: Platform (Cygwin?) GCC version used Logs of verify.pl with -v enabled (to see the full command-lines) The file cci_core/systemc.h is an internal header which is only included through this path. A conflict could only occur, should you add cci_core/ directly to the compiler include path (which is not supported), or if you'd install SystemC below cci_core/ (which would be very weird ;-)). The errors in ex07_Parameter_Information indeed look like the SystemC installation is not correctly resolved. For this, the full command-lines would really help. The error in ex16_User_Defined_Data_Type is indeed a bug (at least before C++14(?)). The fix is to explicitly open the cci namespace around the cci_value_converter specialization in ex16_user_datatype.h. Hope that helps and thanks again, Philipp
  4. thread resets and events

    Hi Fred, synchronous resets are indeed not triggering the process themselves (that's why it's called "synchronous) and instead are only checked when the process is triggered through other means. Typically, this would be a trigger from the static sensitivity (clk.pos() in your case). As @AmeyaVS correctly pointed out, dynamic sensitivity replaces the triggering behavior (not the reset specs). So your synchronous reset would be checked only, when some_signal is de-asserted. Asynchronous resets continue to fire. A polling loop would be the most accurate way to model your design wrt. resets. If you know the reset signals at the point of that wait statement, you can approximate the behavior by waiting for either the signal or the reset (which will then reset the process) wait( some_signal.negedge_event() | rst_n.negedge_event() ); Of course, this might be one clock cycle off. To be correct, you need to have an event that's synchronous to the clock again: sc_event thread_rst_ev; SC_METHOD(thread_sync_reset); sensitive << clk.pos(); // ... void thread_sync_reset() { if (rst_n == false) thread_rst_ev.notify(); } // ... wait( some_signal.negedge_event() | thread_rst_ev ); By the way: a smart wait_until( some_signal == false ), which supports (synchronous) resets and avoids polling internally would be a very useful feature for writing signal-level protocols. Greetings from Duisburg, Philipp
  5. Mingw Compile Issue

    Oh, and after reading the full compiler error, I see that @AmeyaVS is absolute right about the missing SC_BUILD define.
  6. Mingw Compile Issue

    You need to make sure to select the C++ standard (C++03, C++11, C++14) consistently. See this thread for a detailed explanation: Hope that helps, Philipp
  7. Using sc_uint_base directly?

    First of all, we need to distinguish between SystemC in general and its synthesizable subset. Whenever something is not explicitly covered by the current synthesizable subset, it's probably best to include the HLS vendors in the discussion. This almost certainly includes sc_signal<sc_uint_base>. Vendors may support this as signal type, if they can derive the width of the signal (statically) during elaboration. But in a fully generic fabric model, this might be difficult. IIRC, the main difference between SystemC and MyHDL or Chisel is that the latter basically create an explicit "netlist" in memory during elaboration. Basically, the synthesis rules/tool is already embedded in the language (kernel) itself, knowing how to generate the elaborated model to Verilog from memory. In SystemC, a synthesis tool is implemented more like a compiler, i.e. working at the language level directly. These are very different approaches with different benefits and limitations. When you refer to "runtime-defined bitwidths", you certainly mean "elaboration-defined", because the widths cannot change once the simulation has started. But sc_uint_base doesn't know about elaboration/simulation. In order to reduce the risk of width mismatches, you would need a custom channel as suggested by Torsten. But as you said, such custom channels are not supported well by HLS tools. Long story short: Having an "elaboration-sized" signal could definitely help for HLS use cases like yours. The simulation model could be implemented quite easily based on a signal specialization for sc_(u)int_base/sc_(u)nsigned. But as long as HLS tools doesn't support it, its usage would be fairly limited. Have you talked to HLS vendors about this already? Last, but not least, I think that C++17 constexpr, especially in combination with if constexpr and auto return type deduction, will provide most of the required features to write generic "hardware construction code" efficiently. Such models would then automatically be synthesizable by an C++17 capable HLS tool, as the code is evaluated during compile time already.
  8. Difference between TLM 2 and 2.0.1

    Hi Matthias, I would say, this is just an inadvertent editorial change. The normative text still explicitly includes this transition. I'll forward your finding to the Accellera/IEEE WGs to get this fixed in a future revision of IEEE 1666. Thanks for reporting, Philipp
  9. Difference between TLM 2 and 2.0.1

    Can you elaborate a bit more on your question? Figure 28 in IEEE 1666-2011, 15.2.3, shows BEGIN_RESP->TLM_COMPLETED as a valid early completion path? (And yes, 1666-2011 is based on 2.0.1 plus some additional updates).
  10. How exactly sc_main works !!

    This question in mostly about how the linker works on your platform, and not really specific to SystemC. Let me try to give a short summary: Yes, the "main" symbol is needed by the final application For every needed symbol, the linker looks in your object files first If the symbol is present there, the linker picks it up If not, the linker looks in the libraries given by the user (order/lookup is platform-specific) Repeat this for all required symbols (including "sc_main") So, if you define your own "main" in your application, SystemC's "main" will not be picked. This is actually a feature, as you can call "sc_elab_and_sim" manually from your "main" as well, if you want. Hope that helps, Philipp
  11. wait() is not suspending the thread

    Does is make a difference to explicitly qualify wait() with its namespace? sc_core::wait(); If you happen to call unqualified wait() outside of an immediate SystemC module/channel member function, the compiler might accidentally pick up something else coming from a system header on your platform.
  12. before_end_of_elaboration callback

    Because your "analyzer" instance is a local variable in the before_end_of_elaboration function, which gets destructed immediately, when the function returns. So there is no analyzer left to call the callback on later (same holds for the local signal sig2, btw.). You would need to allocate the module dynamically instead. You cannot alter/modify/redefine any existing port binding at any time. You can only add new bindings, including during before_end_of_elaboration. Hope that helps, Philipp
  13. Bug at file sc_trace_file_base.cpp

    I can also add a quote from the Verilog Standard IEEE 1364-2005, $timescale, describing the grammar rules for the timescale support in VCD: So even here, only powers of 10 are allowed.
  14. Bug at file sc_trace_file_base.cpp

    Quoting IEEE 1666-2011, 8.1.2 (color highlighting mine): So I think, the implementation in SystemC 2.3.2 is in line with the SystemC standard. Instead of failing with an assertion, a more explanatory error message would be helpful, of course. Greetings from Duisburg, Philipp
  15. Hi Jarodw, Thanks for your report. I can confirm and reproduce the issue in SystemC 2.3.2. It looks indeed like a regression compared to SystemC 2.3.0/1 that has been introduced by the fix for optionally unbound sockets, see: It seems, the SystemC regression tests didn't cover the hierarchical binding for the multi sockets, so it wasn't caught before the release. Your example can be fixed by changing line 228 in src/tlm_utils/multi_passthrough_target_socket.h: if (unbound && !m_hierarch_bind) return; // ^-- add check for hierarchical binding here Hope that helps, Philipp