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gaurav_brcm

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Posts posted by gaurav_brcm


  1. Hi All,

     

    I wanted to know the usage of get_hdl_path() and get_full_hdl_path(). Any example would be helpful.

    I have added set_hdl_path_root for register block on top level and added add_hdl_path for different registers such as  :

     

    add_hdl_path ('{ '{"RegA", -1 , -1} }); for RegA
    add_hdl_path ('{ '{"RegB", -1 , -1} }); for RegB
     

    And this line in register block :

    this.set_hdl_path_root("top.dut", "RTL");

     

    Now I want to know what HDL path is getting used while doing peek method ?

     

    Thanks,

    Gaurav


  2. Hi,

     

    I want to use in-built UVM RAL cover groups.

    I tried following steps but did not help :

     

    1) Enable coverage building:

         Before building register model, I use following :

         uvm_reg::include_coverage("*",UVM_CVR_ALL);

     

    2) To enable sampling :

        <_regmodel>.set_coverage(UVM_CVR_ALL);

     

    In my regmodel there are two types of cover groups: UVM_CVR_ADDR_MAP in top level register model and UVM_CVR_REG_BITS in individual registers.

     

    I was hoping that UVM_CVR_ALL would enable sampling of all.

     

    I could see cover groups getting built but are not sampled.

     

    Am I missing something ?

     

    Please let me know.

     

    Thanks.


  3. Hi All,

    I am facing an issue:

    One of the register field is configured as :

     
    field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1);
    field_a.set_compare(UVM_NO_CHECK);
     
    While doing a reset test, first I reset model then start test.
     
    But test fails with :

    UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00)

     

    Basically the fields declared as RO and UVM_NO_CHECK goes X ?

     

     

    Any idea what I am missing or doing wrong ?

     

    Thanks.


  4. Thanks a lot for your reply.

    By changing constraint , I meant changing some values of field .

    For eg :

    class base_seq extends uvm_sequence; 

     packet pkt;

     `uvm_do_with (pkt.addr == a);

    endclass

     

    class top_seq extends uvm_sequence (virtual sequence)

      base_seq seq;

      `uvm_do_on_with(seq, p_sequencer.sqr { 

                                   pkt.addr == b; } )

    endclass

     

    So in this case pkt.addr == b does not work and there is constraint failure.

     

    What is the best way now ??

     

    Thanks and Regards,

    GG

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